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vmds-10210 revision 4.1 september 2009 vsc8601 10/100/1000base-t phy with rgmii mac interface datasheet
revision 4.1 september 2009 page 2 vitesse corporate headquarters 741 calle plano camarillo, california 93012 united states www.vitesse.com copyright? 2005?2007, 2009 by vitesse semiconductor corporation vitesse semiconductor corporation (?vitesse?) retains the right to make changes to its products or specifications to improve perf ormance, reliability or manufacturability. all information in this document, includin g descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. while the information furn ished herein is held to be accurate and reliable, no responsibility will be assumed by vitesse for its use. furthermore, the information contained herein does not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer. vitesse products are not intended for use in products or applications, including, but not limited to, medical devices (including life support and implantable medical devices), nuclear products, or other safety-critical uses where failure of a vitesse product could reasonably be expected to result in person al injury or death. anyone using a vitesse product in such an application without express written consent of an officer of vitesse does so at their own risk, and agrees to fully indemnify vitesse for any damages that may result from such use or sale. safety of laser products, iec 60825. while vitesse products support iec 60825, use of vitesse products does not ensure compliance to iec 60825. buyers are responsible for ensuring compliance to iec 60825. buyers must fully indemnify vitesse for any damages resulting from non-compliance to iec 60825. vitesse semiconductor corporation is a regi stered trademark. all other products or service names used in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. all other trademarks or registered trademarks ment ioned herein are the property of their respective holders.
vsc8601 datasheet contents revision 4.1 september 2009 page 3 contents revision history ..........................................................................................9 1 introduction.....................................................................................13 2 product overview.............................................................................14 2.1 features ........................................................................................................... 14 2.2 applications....................................................................................................... 15 2.3 block diagram ................................................................................................... 16 3 functional descriptio ns....................................................................17 3.1 interface and media............................................................................................ 17 3.2 mac interface.................................................................................................... 17 3.2.1 mac resistor calibration .......................................................................... 17 3.2.2 rgmii mac interface mode ...................................................................... 17 3.3 cat5 media interface .......................................................................................... 18 3.4 cat5 auto-negotiation ........................................................................................ 19 3.5 manual mdi/mdi-x setting .................................................................................. 20 3.6 automatic crossover and polarity detection ........................................................... 20 3.7 link speed downshift ......................................................................................... 21 3.8 transformerless ethernet..................................................................................... 21 3.9 ethernet inline powered devices .......................................................................... 21 3.10 actiphy power management................................................................................. 23 3.10.1 low-power state .................................................................................... 24 3.10.2 link partner wake-up state ..................................................................... 25 3.10.3 normal operating state ........................................................................... 25 3.11 serial management interface ........................ ....................................................... 25 3.11.1 smi frames ........................................................................................... 25 3.11.2 smi interrupts ....................................................................................... 27 3.12 led interface .................................................................................................... 28 3.12.1 simple or enhanced led method............................................................... 28 3.12.2 led modes............................................................................................. 28 3.12.3 led behavior ......................................................................................... 30 3.13 testing features................................................................................................. 30 3.13.1 ethernet packet generator (epg) .............................................................. 30 3.13.2 crc counters......................................................................................... 31 3.13.3 far-end loopback ................................................................................... 31 3.13.4 near-end loopback ................................................................................. 32 3.13.5 connector loopback................................................................................ 32 3.13.6 veriphy cable diagnostics........................................................................ 33 3.13.7 ieee 1149.1 jtag boundary scan ............................................................. 33 3.13.8 jtag instruction codes............................................................................ 34 3.13.9 boundary-scan register cell order............................................................ 36 4 configuration ...................................................................................37 4.1 registers........................................................................................................... 37 4.1.1 reserved registers ................................................................................. 38 4.1.2 reserved bits ......................................................................................... 38 4.2 ieee standard and main registers ........................................................................ 38 4.2.1 mode control ......................................................................................... 39 4.2.2 mode status........................................................................................... 40
vsc8601 datasheet contents revision 4.1 september 2009 page 4 4.2.3 device identification ............................................................................... 41 4.2.4 auto-negotiation advertisement ............................................................... 41 4.2.5 link partner auto-negotiation capability ..... ................ ............ ........... ........ 42 4.2.6 auto-negotiation expansion ..................................................................... 43 4.2.7 transmit auto-negotiation next page......... ................................................ 43 4.2.8 auto-negotiation link partner next page receive ........................................ 44 4.2.9 1000base-t control................................................................................ 44 4.2.10 1000base-t status................................................................................. 45 4.2.11 main registers reserved addresses ........................................................... 45 4.2.12 1000base-t status extension 1................................................................ 45 4.2.13 100base-tx status extension .................................................................. 46 4.2.14 1000base-t status extension 2................................................................ 46 4.2.15 bypass control ....................................................................................... 47 4.2.16 receive error counter ............................................................................. 48 4.2.17 false carrier sense counter ..................................................................... 48 4.2.18 disconnect counter................................................................................. 49 4.2.19 extended control and status .................................................................... 49 4.2.20 extended phy control set 1 ..................................................................... 50 4.2.21 extended phy control set 2 ..................................................................... 50 4.2.22 interrupt mask ....................................................................................... 51 4.2.23 interrupt status ..................................................................................... 52 4.2.24 led control ........................................................................................... 52 4.2.25 auxiliary control and status ............ ........... .......... ........... ........... ........ ...... 53 4.2.26 delay skew status.................................................................................. 54 4.2.27 reserved address space .......................................................................... 54 4.3 extended page registers ..................................................................................... 55 4.3.1 extended page access ............................................................................. 56 4.3.2 enhanced led method select ................................................................... 56 4.3.3 enhanced led behavior ........................................................................... 57 4.3.4 crc good counter .................................................................................. 58 4.3.5 mac resistor calibration control ............. .................................................. 58 4.3.6 extended phy control 3........................................................................... 59 4.3.7 eeprom interface status and control ........................................................ 59 4.3.8 eeprom data read/write ........................................................................ 60 4.3.9 extended phy control 4........................................................................... 60 4.3.10 reserved extended registers ................................................................... 61 4.3.11 extended phy control 5........................................................................... 61 4.3.12 rgmii skew control................................................................................ 62 4.3.13 ethernet packet generator (epg) control 1 ................................................ 63 4.3.14 ethernet packet generator control 2 ......................................................... 64 4.4 cmode ............................................................................................................. 64 4.4.1 cmode pins and related functions ........... ................................................ 64 4.4.2 functions and related cmode pins ........................................................... 65 4.4.3 cmode resistor values............................................................................ 65 4.5 eeprom............................................................................................................ 66 4.5.1 eeprom contents description .................................................................. 66 4.5.2 read/write access to the eeprom ............................................................ 67 5 electrical specifications ...................................................................69 5.1 dc characteristics .............................................................................................. 69 5.1.1 vddio at 3.3 v ...................................................................................... 69 5.1.2 vddio at 2.5 v ...................................................................................... 70 5.2 current consumption.......................................................................................... 70 5.2.1 consumption with 1000base-t link .......................................................... 70 5.2.2 consumption with 100base-tx link .......................................................... 71
vsc8601 datasheet contents revision 4.1 september 2009 page 5 5.2.3 consumption with 10base-t link.............................................................. 72 5.2.4 consumption with no link and actiphy enabled .......................................... 73 5.2.5 consumption with no link and actiphy di sabled ......................................... 73 5.2.6 consumption in power-down mode............................................................ 74 5.2.7 consumption in reset state ..................................................................... 75 5.3 ac characteristics .............................................................................................. 75 5.3.1 reference clock input ............................................................................. 76 5.3.2 clock output .......................................................................................... 76 5.3.3 jtag interface ....................................................................................... 77 5.3.4 smi interface ......................................................................................... 77 5.3.5 device reset .......................................................................................... 78 5.3.6 rgmii uncompensated ............................................................................ 80 5.3.7 rgmii compensated ............................................................................... 81 5.4 operating conditions .......................................................................................... 82 5.5 stress ratings ................................................................................................... 83 6 pin descriptions ...............................................................................84 6.1 pin diagram ...................................................................................................... 84 6.2 pins by function................................................................................................. 85 6.2.1 twisted pair interface .............................................................................. 85 6.2.2 rgmii mac interface .............................................................................. 86 6.2.3 serial management interface (smi)........................................................... 87 6.2.4 jtag ..................................................................................................... 88 6.2.5 miscellaneous......................................................................................... 88 6.2.6 power supply ......................................................................................... 89 6.2.7 power supply and associated function....... ................................................ 90 6.3 pins by name .................................................................................................... 91 6.4 pins by number ................................................................................................. 92 7 package information........................................................................93 7.1 package drawing................................................................................................ 93 7.2 thermal specifications ........................................................................................ 95 7.3 moisture sensitivity ............................................................................................ 95 8 design considerations .....................................................................96 8.1 rx_clk can reach as high as 55% duty cycle ...................................................... 96 8.2 first smi write fails after software reset .............................................................. 96 8.3 link-up issue in forced 100base-tx mode ............................................................ 96 8.4 default 10base-t settings are marginal and cause mau test failure.......................... 97 8.5 on-chip pull-up resistor violation................. ........................................................ 99 8.6 setting the internal rgmii timing compensation value ........................................... 99 8.7 10base-t harmonics at 30 mhz and 50 mhz marg inally violate specification .............. 99 8.8 voltage overshoot when using on-chip switchin g regulator.................................. 100 8.9 long link-up times caused by noise on the twisted pair interface ......................... 100 8.10 high vdd33 and low vddiomac supply ............................................................. 101 9 ordering information .....................................................................102
vsc8601 datasheet contents revision 4.1 september 2009 page 6 figures figure 1. typical application...................................................................................... 14 figure 2. high-level block diagram ............................................................................ 16 figure 3. rgmii to cat5 block diagram ...................................................................... 17 figure 4. rgmii mac interface .................................................................................. 18 figure 5. cat5 media interface .................................................................................. 19 figure 6. inline powered ethernet switch diagram ....................................................... 22 figure 7. actiphy state ............................................................................................ 24 figure 8. smi read frame ........................................................................................ 26 figure 9. smi write frame........................................................................................ 26 figure 10. mdint configured as an open-drain (active-low) pin..................................... 27 figure 11. mdint configured as an open-source (active-high) pin .................................. 27 figure 12. far-end loopback ...................................................................................... 32 figure 13. near-end loopback .................................................................................... 32 figure 14. connector loopback ................................................................................... 32 figure 15. test access port and boundary-scan architecture ........................................... 34 figure 16. register space diagram.............................................................................. 37 figure 17. eeprom read and write register flow .......................................................... 68 figure 18. jtag interface timing ................................................................................ 77 figure 19. smi interface timing .................................................................................. 78 figure 20. reset timing ............................................................................................. 79 figure 21. rgmii uncompensated timing ..................................................................... 81 figure 22. rgmii compensated timing ........................................................................ 82 figure 23. pin diagram .............................................................................................. 84 figure 24. package drawing ....................................................................................... 94
vsc8601 datasheet contents revision 4.1 september 2009 page 7 tables table 1. interface and media ................................................................................... 17 table 2. supported mdi pair combinations ................................................................ 21 table 3. led mode and function summary ................................................................ 28 table 4. jtag device identification register descr iption .............................................. 35 table 5. jtag interface instruction codes ................................................................. 35 table 6. ieee 802.3 standard registers .................................................................... 38 table 7. main registers ........................................................................................... 38 table 8. mode control, address 0 (0x00)................................................................... 39 table 9. mode status, address 1 (0x01) .................................................................... 40 table 10. identifier 1, address 2 (0x02)...................................................................... 41 table 11. identifier 2, address 3 (0x03)...................................................................... 41 table 12. device auto-negotiation advertisement, address 4 (0x04) .............................. 41 table 13. auto-negotiation link partner ability, ad dress 5 (0x05).... ............ ........... ........ 42 table 14. auto-negotiation expansion, address 6 (0x06)............................................... 43 table 15. auto-negotiation next page transmit, a ddress 7 (0x07) .................................. 43 table 16. auto-negotiation lp next page receive, address 8 (0x08) ............................... 44 table 17. 1000base-t control, address 9 (0x09) ......................................................... 44 table 18. 1000base-t status, address 10 (0x0a) ........................................................ 45 table 19. 1000base-t status extension 1, address 15 (0x0f) ....................................... 45 table 20. 100base-tx status extension, address 16 (0x10) .......................................... 46 table 21. 1000base-t status extension 2, address 17 (0x11) ....................................... 46 table 22. bypass control, address 18 (0x12)............................................................... 47 table 23. receive error counter, address 19 (0x13) ..................................................... 48 table 24. false carrier sense counter, address 20 (0x14) ............................................. 48 table 25. disconnect counter, address 21 (0x15)......................................................... 49 table 26. extended control and status, address 22 (0x16) ........................................... 49 table 27. extended phy control 1, address 23 (0x17) .................................................. 50 table 28. extended phy control 2, address 24 (0x18) .................................................. 50 table 29. interrupt mask, address 25 (0x19)............................................................... 51 table 30. interrupt status, address 26 (0x1a)............................................................. 52 table 31. led control, address 27 (0x1b)................................................................... 52 table 32. auxiliary control and status, address 28 (0x1c) ........ ........... ........... ........ ...... 53 table 33. delay skew status, address = 29 (0x1d)...................................................... 54 table 34. extended registers page space.................................................................... 55 table 35. extended page access, address 31 (0x1f)..................................................... 56 table 36. enhanced led method select, address 16e (0x10) ......................................... 56 table 37. available led mode settings........................................................................ 56 table 38. enhanced led behavior, address 17e (0x11) ................................................. 57 table 39. crc good counter, address 18e (0x12) ........................................................ 58 table 40. mac resistor calibration control, address 19e (0x13)..................................... 58 table 41. extended phy control 3, address 20e (0x14)................................................. 59 table 42. eeprom interface status and control, address 21e (0x15).............................. 59 table 43. eeprom read or write, address 22e (0x16) .................................................. 60 table 44. extended phy control 4, address 23e (0x17)................................................. 60 table 45. extended phy control 5, address 27e (0x1b) ................................................ 61 table 46. rgmii skew control, address 28e (0x1c) ..................................................... 62 table 47. epg control register 1, address 29e (0x1d).................................................. 63 table 48. epg control register 2, address 30e (0x1e) .................................................. 64 table 49. cmode configuration pins and device func tions ............................................ 64 table 50. device functions and associated cmode pi ns ................................................ 65 table 51. cmode resistor values and resultant bit settings .......................................... 65 table 52. eeprom configuration contents................................................................... 67 table 53. dc characteristics for vdd33, vddiomac, or vddiomicro at 3.3 v ................ 69
vsc8601 datasheet contents revision 4.1 september 2009 page 8 table 54. dc characteristics for vddiomac or vddiomicro at 2.5 v............................. 70 table 55. current consumption: 1000base-t, regula tor enabled ................................... 70 table 56. current consumption: 1000base-t, regula tor disabled................................... 71 table 57. current consumption: 100base-tx, regulator enabled ................................... 71 table 58. current consumption: 100base-tx, regula tor disabled .................................. 71 table 59. current consumption: 10base-t, regulator enabled ....................................... 72 table 60. current consumption: 10base-t, regulato r disabled ...................................... 72 table 61. current consumption: no link, actiphy enabled, regulator enabled ................. 73 table 62. current consumption: no link, actiphy enabled, regulator disabled ................ 73 table 63. current consumption: no link, actiph y disabled, regulator enabled ................ 73 table 64. current consumption: no link, actiph y disabled, regulator disabled................ 74 table 65. current consumption: power-down, regula tor enabled................................... 74 table 66. current consumption: power-down, regula tor disabled .................................. 75 table 67. current consumption: reset state ............................................................... 75 table 68. ac characteristics for refclk input ............................................................. 76 table 69. ac characteristics for refclk input with 25 mhz clock input .......................... 76 table 70. ac characteristics for the clkout pin .......................................................... 76 table 71. ac characteristics for the jtag interface... .................................................... 77 table 72. ac characteristics for the smi interface ........................................................ 77 table 73. ac characteristics for device reset .............................................................. 78 table 74. ac characteristics for rgmii uncompensated ................................................ 80 table 75. ac characteristics for rgmii compensated.................................................... 81 table 76. recommended operating conditions............................................................. 82 table 77. stress ratings ........................................................................................... 83 table 78. pin type symbols ....................................................................................... 85 table 79. twisted pair interface pins........................................................................... 85 table 80. rgmii mac interface pins ........................................................................... 86 table 81. smi pins ................................................................................................... 87 table 82. jtag pins.................................................................................................. 88 table 83. miscellaneous pins ..................................................................................... 88 table 84. power supply pins...................................................................................... 89 table 85. power supply pins and associated function pins............................................. 90 table 86. thermal resistances................................................................................... 95 table 87. ordering information................................................................................ 102
vsc8601 datasheet revision history revision 4.1 september 2009 page 9 revision history this section describes the changes that were implemented in this document. the changes are listed by revision, starting with the most current publication. revision 4.1 revision 4.1 of this datasheet was publishe d in september 2009. in revision 4.1 of the document, design considerations were added. for more information, see ?design considerations,? page 96 . revision 4.0 revision 4.0 of this datasheet was published in november 2007. the following is a summary of the changes implemented in the datasheet: ? the vsc8601kn package was removed. VSC8601XKN remains available. ? the electrostatic discharge voltage values were added. for charged device model, it is 500. for human body model, it is 1500. ? the moisture sensitivity is now specified as level 3. ? in the jumbo packet register settings (28e.11:10), the packet lengths were updated. ? in several current consumption specifications, the values for total power at 2.5 v were corrected. the previous values were slightly elevated. ? in the dc characteristics for v ddio at 3.3 v, both the input and output leakage current parameters (i ileak and i oleak ) were increased from 36 a to 43 a. ? in the dc characteristics for v ddio at 2.5 v, the minimum input high voltage (v ih ) was increased from 1.7 v to 2.0 v. both the input and output leakage current parameters (i ileak and i oleak ) were increased from 25 a to 35 a. ? current consumption specifications were added for both the power-down mode and the reset state. ? in the ac characteristics for the clkout pin, the duty cycle (% duty ) was modified from 40% minimum to 44% minimum and from 60% maximum to 56% maximum. also, the total jitter (j clk ) was raised from 491 ps maximum to 600 ps maximum, with the qualifier ?time interval error? added to the condition. ? in the smi specifications, the mdc rise and fall times were corrected from minimum values to maximum values. ? for the device reset rise time specification, a condition was added that it is measured from a 10% level to a 90% level. ? in the ac characteristics for rgmii unc ompensated, the 1000base-t duty cycle (t duty1000 ) was separated into two sets of values. in the first set, the values remain the same, but the added condition is: at room temperature and nominal supply and
vsc8601 datasheet revision history revision 4.1 september 2009 page 10 register 28e.13:12 set to 10 or 11. in the second set, the minimum is 40% and the maximum is 60% and the condition is: register 28e.13:12 set to 00 or 01. ? in the ac characteristics for rgmii compensated, all of the setup and hold times were modified from 0 ns maximum to 3 ns maximum. ? in the description of pin mdio, the type was corrected from open drain (od) to input and output (i/o). ? the pllmode pin description was updated with additional clocking information. if a crystal or an external 25 mhz clock is used, pllmode must be pulled low. if an external 125 mhz clock is used, pllmode must be pulled high. ? a design guideline was added regarding writes from the serial management interface (smi) after a software reset. ? a design guideline was added regarding de lays in the link-up process while in the forced 100base-tx mode with the automatic mdi/mdi-x detection feature enabled. ? the following design guidelines were removed, because they no longer apply to the device: remote fault status; dsp optimizati on script required; default port type incorrect; and core 1.2 v supply needs to meet specific range. revision 2.2 revision 2.2 of this datasheet was publishe d in july 2006. the following is a summary of the changes implemented in the datasheet: ? in the inline powered ethernet switch di agram, a reference to ?sgmii interface? was corrected to ?rgmii interface.? ? in the description of crc counters, the crc good counter?s highest value was corrected from 10,000 to 9,999 packets, after which the counter clears. ? the device revision number definition was updated from 0000 to 0001 in the identifier 2 register (address 3) and the jtag device identification. ? in the dc characteristics for v dd33 , v ddiomac , or v ddiomicro at 3.3 v, the output leakage (i oleak ) was changed to match the same values as the input leakage (i ileak ) with the same condition (internal resist or included). specifically, the values were changed from ?10 a minimum and 10 a maximum to ?36 a minimum and 36 a maximum. ? in the dc characteristics for v ddiomac or v ddiomicro at 2.5 v, the output leakage (i oleak ) was changed to match the same values as the input leakage (i ileak ) with the same condition (internal resistor in cluded). specifically, the values were changed from ?10 a minimum and 10 a maximum to ?25 a minimum and 25 a maximum. ? in the dc characteristics for v ddiomac or v ddiomicro at 2.5 v, the output high voltage parameter (v oh ) incorrectly stated i oh = 1.0 ma as a condition. it is now corrected to the condition i oh = ?1.0 ma. ? for all the current consumption specifications with the on-chip switching regulator enabled, the specification values for i vdd12 and i vdd12a were removed because
vsc8601 datasheet revision history revision 4.1 september 2009 page 11 they were inadvertently added in a pr ior revision of this document. the i vdd12 and i vdd12a values are kept for current consumption with the regulator disabled. ? for the 100base current consumption spec ifications, all references to the speed were corrected from 100base-x to 100base-tx. ? in the ac characteristics for the clkout pin, the total jitter specifications were added. they are 217 ps typical and 491 ps maximum. ? for device reset, both the reset characte ristics and timing diagram were updated to include new parameters: reset rise time (t rst_rise ) and supply stable time (t vddstable ). ? in the stress ratings, the power supply voltage parameter was removed because it was redundant. ? in the pin description for tx_clk, the rate was clarified to be 2.5 mhz for 10 mbps mode, 25 mhz for 100 mbps mode, or 125 mhz for 1000 mbps mode. ? the errata item ?rx_clk can reach as high as 55% duty cycle? remains in effect but all other errata items no longer apply to the latest part revision. revision 2.1 revision 2.1 of this datasheet was publis hed in february 2006. the following is a summary of the changes implemented in the datasheet: ? in the high-level block diagram, representation of the xtal pin was corrected from ?xtal 1/2? to ?xtal1? and ?xtal2.? ? in the rgmii to cat5 block diagram, the interface name was corrected from gmii to rgmii. ? new information was added about how to manually force the device to use mdi/mdi-x. ? the vsc8601 device switches between the low-power state and lp wake-up state every two seconds; the rate is not pr ogrammable, as was originally stated. ? in the link partner wake-up state, the device sends flp bursts for two seconds; they are not limited to three bursts, as was originally stated. ? in the description of the phy address for the serial management interface (smi), the physical address was corrected from 3:0 to 4:0. ? for the enhanced led method, controlled by mii register 16e, two of the led modes have changed. mode 11, tx activity , and mode 13, rx activity, are now both reserved. ? in the description of the far-end loopback testing feature, the controlling register bit was corrected from 23.3 to 27e.10. ? for the jtag interface instructions ex test and sample/preload, the values for register width were modified from tbd to 45. ? for the mode control register (address 0), when bit 11 (power-down) is set, rgmii in-band signaling will not function.
vsc8601 datasheet revision history revision 4.1 september 2009 page 12 ? in the identifier 2 register (address 3), which enables device identification, the default for bits 9:4 was modified from tbd to 000010. ? in the led control register (address 27), the name for bits 2 and 1 was corrected from ?link/activity? to simply ?activity.? ? in the actiphy control (address 20e), bit 5 was reassigned from being reserved to being the mac rx_clk disable parameter. ? in the extended phy control 4 register (address 23e), all the bit settings were mistakenly omitted. they are now restored. ? in the extended phy control 5 register (address 27e), the settings have changed for bits 8:6 and 5:3 (100base-tx and 1000base-t transmitter amplitude control). for bits 8:6 (100base-tx), the setting 011 changed from +5 amplitude to reserved, making bit setting 010 (+4 amplitude) the largest. for bits 5:3 (1000base-t), the setting 011 changed from +3 amplitude to reserved, making bit setting 010 (+2 amplitude) the largest. ? for added clarity, the table that lists de vice functions and related cmode pins now references the associated register and bit for each function. ? for the eeprom configuration contents table, some address locations were added and the introductory text was corrected. ? for the dc electrical specifications with vddio at 3.3 v and with vddio at 2.5 v, an additional condition was added. the specif ications may be considered valid only when vddreg = 3.3 v. ? the current consumption specifications were replaced with a new set of specifications. ? in the recommended operating conditions, the minimum and maximum values were modified for the vddiomicro, vddi omac, and vdd33 parameters at 3.3 v. for all of these parameters, the minimum changed from 3.13 v to 3.0 v and the maximum changed from 3.47 v to 3.6 v. the vddreg parameter was added to the recommended operating conditions. ? in the stress ratings, a new rating was added for the vddreg parameter. ? an errata section was added. revision 2.0 revision 2.0 of this datasheet was published in december 2005. this was the first publication of the document.
vsc8601 datasheet introduction revision 4.1 september 2009 page 13 1introduction this document consists of descriptions an d specifications for both functional and physical aspects of the vsc8601 10/100/1000base-t phy with rgmii mac interface. in addition to the datasheet, vitesse mainta ins an extensive device-specific library of support and collateral materials that you may find useful in developing your own product. depending upon the vitesse device, this library may include: ? software development kits with sample commands and scripts ? reference designs showing the vitesse device built in to applications in ways intended to exploit its relative strengths ? presentations highlighting the operational features and specifications of the device to assist in developing your own product road map ? input/output buffer information specificatio n (ibis) models to help you create and support the interfaces available on the particular vitesse product ? application notes that provide detailed descriptions of the use of the particular vitesse product to solve real-world problems ? white papers published by industry expe rts that provide ancillary and background information useful in developing produc ts that take full advantage of vitesse product designs and capabilities ? user guides that describe specific techniques for interfacing to the particular vitesse products visit and register as a user on the vitesse web site to keep abreast of the latest innovations from research and developmen t teams and the most current product and application documentation. the address of the vitesse web site is www.vitesse.com.
vsc8601 datasheet product overview revision 4.1 september 2009 page 14 2 product overview the vsc8601 device is a low-power gigabit ethernet (gbe) transceiver ideal for gigabit lan-on-motherboard applications. the device?s compact, plastic low-profile quad flat package (lqfp) with an exposed pad is op timal for footprint-sensitive applications. vitesse?s mixed signal and digital signal processing (dsp) architecture assures robust performance. it supports both half-duple x and full-duplex 10base-t, 100base-tx, and 1000base-t communication speeds over catego ry 5 (cat5) unshielded twisted pair (utp) cable at distances greater than 140 m, displaying excellent tolerance to next, fext, echo, and other types of ambient en vironment and system electronic noise. the following illustration shows a high-level , generic view of a vsc8601 application. figure 1. typical application 2.1 features this section lists key aspects of the vsc8601 device functionality and design that distinguish it from similar products: ? 10/100/1000base-t phy with indust ry?s lowest power consumption. ? compliant with ieee 802.3 (10base-t, 100base-tx, 1000base-t) specifications. ? supports rgmii versions 1.3 and 2.0 (2.5 v, 3.3 v) mac interface. ? low emi line driver with integrated line side termination resistors. ? up to 16 kb jumbo frame support in all speeds. ? three programmable direct drive leds. ? suite of test modes, including loopback paths, ethernet packet generators, and crc counters. ?the veriphy ? suite provides extensive network cable information such as cable length, termination status, and open/short fault location. ?actiphy tm power saving modes. ? advanced power management complies with wake-on-lan tm and pci2.2 power requirements. vsc8601 10/100/1000base-t transceiver rj45+magnetics rgmii management i/f (mdc / mdio) 10/100/1000base-t mac, switching asic, or network processor 25 mhz 3.3 v
vsc8601 datasheet product overview revision 4.1 september 2009 page 15 ? legacy power-over-ethernet (poe) support. ? powered by a single 3.3 v supply by usin g the optional on-chip switching regulator. ? ieee 1149.1 jtag boundary-scan support. ? 10 mm 10 mm, 64-pin, plastic lqfp package with an exposed pad. 2.2 applications suggested applications for the vsc8601 device include: ? lan-on-motherboards, nics, and mobile pcs ? iscsi and toe applications ? workgroup and desktop switches and routers ? gigabit ethernet san, nas, and man systems ? network-enabled devices such as printers, ip phones, and gaming appliances ?atca tm 3.0 and picmg tm 2.16 ethernet backplane applications
vsc8601 datasheet product overview revision 4.1 september 2009 page 16 2.3 block diagram the following illustration shows the primary functional blocks of the vsc8601 device. figure 2. high-level block diagram led interface 10/100/ 1000base-t pcs led[2:0] clkout xtal1 txd[3:0] tx_ctl rxd[3:0] rx_ctl rgmii mac interface jumbo packet fifo txvpa txvna txvpb txvnb txvpc txvnc txvpd txvnd pll jtag management and control interface tdi ntrst tms tck tdo cmode[3:0] nreset eeclk eedat mdint mdio mdc mdi twisted pair interface 10/100/ 1000base-t pma ref_filt ref_rext tx_clk rx_clk power regulation reg_out reg_en nsreset mdi reference xtal2
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 17 3 functional descriptions this section provides detailed information about how the vsc8601 device works, what configurations and operational features are available, and how to test its functions. it includes descriptions of the various device interfaces and how to set them up. 3.1 interface and media the vsc8601 device operates with the interf ace and media shown in the following table and illustration. figure 3. rgmii to cat5 block diagram 3.2 mac interface the vsc8601 supports rgmii versions 1.3 and 2.0 (2.5 v, 3.3 v) mac interface. 3.2.1 mac resistor calibration to simplify board design, the vsc8601 mac interface uses simplipin tm outputs that can self-calibrate to a desired impedance characteristic to eliminate the need for series termination resistors. by default, th ese rx output pins calibrate to 50 . in addition, mii register 19e, bits 15:14 can be used to select different target impedances. for more information, see ?mac resistor calibration control,? page 58. 3.2.2 rgmii mac interface mode the rgmii interface can support all three speeds (10 mbps, 100 mbps, and 1000 mbps) and is used as an interface to an rgmii-compatible mac. table 1. interface and media operating mode mac interface supported media rgmii - cat5 rgmii 10/100/1000base-t mac cat5 rgmii vsc8601 cat5 link partner
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 18 figure 4. rgmii mac interface 3.3 cat5 media interface the twisted pair interface on the vsc860 1 is compliant with the ieee802.3-2000 specifications for cat5 media. the vsc8601, unlike other gigabit phys, has all passive components (required to connect the phy? s cat5 interface to an external 1:1 transformer) fully integrated into the de vice. the connection of the twisted pair interface is shown in the following figure. rgmii mac simpliphy txd[3] txd[2] txd[1] txd[0] tx_clk tx_ctl rxd[3] rxd[2] rxd[1] rxd[0] rx_clk rx_ctl td[3] td[2] td[1] td[0] txc tx_ctl rd[3] rd[2] rd[1] rd[0] rxc rx_ctl r t r t r t r t r t r t 50 50 50 50 50 50
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 19 figure 5. cat5 media interface 3.4 cat5 auto-negotiation the vsc8601 device supports tw isted pair auto-negotiation as defined by clause 28 of the ieee standard 802.3-2000. the auto-negotiation process consists of the evaluation of the advertised capabilities of the phy and its link partner to determine the best possible operating mode, throughput speed, duplex configuration, and master or slave operating modes in the case of 1000base-t setups. auto-negotiation also allows a connected mac to communicate with its link partner mac through the vsc8601 device using the optional ?next pages,? which set attributes that may not otherwise be defined by the ieee standard. in installations where the cat5 link partner does not support auto-negotiation, the vsc8601 automatically switches to use paralle l detection to select the appropriate link speed. clearing vsc8601 device register 0, bit 12 disables clause 28 twisted-pair auto-negotiation. if auto-negotiation is disa bled, the state of register bits 0.6, 0.13, txvp_a_n 1 2 3 6 4 5 7 8 rj-45 a+ a- b+ b- c+ c- d+ d- simpliphy 1000pf, 2kv 75 75 75 75 0.1 f 0.1 f 0.1 f 0.1 f txvn_a_n txvp_b_n txvn_b_n txvp_c_n txvn_c_n txvp_d_n txvn_d_n transformer
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 20 and 0.8 determine the device operating spee d and duplex mode. for more information about configuring auto-negotiation, see ?ieee standard and main registers,? page 38. 3.5 manual mdi/mdi-x setting as an alternative to automatic mdi/mdi-x de tection (using hp auto-mdix technology), you can force the phy to select mdi or mdi-x using the following scripts. format: phywrite ( register(dec), data(hex) ) phywritemask ( register(dec), data(hex), mask(hex) ) to force mdi: phywrite ( 31, 0x2a30 ) phywritemask ( 5, 0x0010, 0x0018 ) phywrite ( 31, 0x0000 ) to force mdi-x: phywrite ( 31, 0x2a30 ) phywritemask ( 5, 0x0018, 0x0018 ) phywrite ( 31, 0x0000 ) to resume mdi/mdi-x setting based on register 18, bits 7 and 5: phywrite ( 31, 0x2a30 ) phywritemask ( 5, 0x0000, 0x0018 ) phywrite ( 31, 0x0000 ) 3.6 automatic crossover and polarity detection for trouble-free configuration and management of ethernet links, the vsc8601 device includes a robust, automatic, media-dependent and crossed media-dependent detection feature, hp auto-mdix, in all of its three available speeds (10base-t, 100base-t, and 1000base-t). the function is fu lly compliant with clause 40 of the ieee standard 802.3-2002. additionally, the device detects and corrects polarity errors on all mdi pairs?a useful capability that exceeds the requirements of the standard. both hp auto-mdix detection and polarity correction are enabled in the device by default. the default settings are adjustable using device register bits 18.5:4. status bits for each of these functions are located in register 28.
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 21 the vsc8601 device?s algorithm for hp auto -mdix successfully detects, corrects, and operates with any of the mdi wiring pair combinations listed in the following table. note the vsc8601 device can be configured to perform hp auto-mdix even when its auto-negotiation feature is disabled (setting register 0.12 to 0) and the link is forced into 10/100 speeds. to enable this feature, set register 27e.15 = 0. 3.7 link speed downshift for operation in cabling environments that are incompatible with 1000base-t, the vsc8601 device provides an automatic link speed ?downshift? option. when enabled, the device automatically changes its 1000b ase-t auto-negotiation advertisement to the next slower speed after a set number of failed attempts at 1000base-t. this is useful in networks using older cable installations that may include only pairs a and b and not pairs c and d. to configure and monitor link speed downshifting, use register bits 20e.4:1. for more information, see ?extended phy control set 1,? page 50. 3.8 transformerless ethernet the cat5 media interface supports 10/100/1000bt ethernet for backplane applications such as those specified by the picmg tm 2.16 and atca tm 3.0 specifications for eight-pin channels. with proper ac coupling, the typical cat5 transformer can be removed and replaced with capacitors. 3.9 ethernet inline powered devices the vsc8601 device can detect inline powered devices in ethernet network applications. its inline powered detection capa bility can be part of a system that allows for ip-phone and other devices, such as wireless access points, to receive power directly from their ethernet cable, similar to office digital phones receiving power from a private branch exchange (pbx) office swit ch over the telephone cabling. this can eliminate the need for an ip-phone to have an external power supply. it also enables the inline powered device to remain active during a power outage (assuming the ethernet switch is connected to an uninterrupted power supply, battery, back-up power generator, or some other uninterruptible power source). for more information about inline powered device detection, visit the cisco web site at www.cisco.com. table 2. supported mdi pair combinations rj-45 pin pairings 1, 23, 64, 57, 8mode a b c d normal mdi b a d c normal mdi-x a b d c normal mdi with pair swap on c and d pair b a c d normal mdi-x with pair swap on c and d pair
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 22 the vsc8601 device is compatible with switch designs that are intended for use in systems that supply power to data terminal equipment (dte) using the mdi or twisted pair cable, as described in clause 33 of the ieee standard 802.3af. the following illustration shows an example of this type of application. figure 6. inline powered et hernet switch diagram the following procedure describes the process that an ethernet switch must perform to process inline power requests made by a link partner (lp) that is, in turn, capable of receiving inline power. 1. enable the inline powered device detect ion mode on each vsc8601 phy using its serial management interface. set register bit 23e.10 to 1. 2. ensure that the vsc8601 device auto-negotiation enable bit (register 0.12) is also set to 1. in the application, the device sends a special fast link pulse (flp) signal to the lp. reading register bit 23e.9:8 returns 00 during the search for devices that require power-over-ethernet (poe). 3. the vsc8601 phy monitors its inputs for th e flp signal looped back by the lp. an lp capable of receiving poe will loopback the flp pulses when it is in a powered-down state. this is reported when vsc8601 device register bit 23e.9:8 reads back 01. it can also be verified as an inline power detection interrupt by smi control processor gigabit switch phy_0 rgmii interface phy_1 x-former rj-45 i/f phy_n rj-45 i/f x-former rj-45 i/f inline power supply unit cat5 x-former
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 23 reading vsc8601 device register bit 26.9, which should be a 1, and which is subsequently cleared and the inte rrupt de-asserted after the read. if an lp device does not loop back the flp after a specific time, vsc8601 device register bit 23e.9:8 automatically resets to 10. 4. if the vsc8601 phy reports that the lp n eeds poe, the ethernet switch must enable inline power on this port, externally of the phy. 5. the phy automatically disables inline powered device detection if the vsc8601 device register bit 23e.9:8 automatically resets to 10, and then automatically changes to its normal auto-negotiation process. a link is then auto-negotiated and established when the link status bit is set (register bit 1.2 is set to 1). 6. in the event of a link failure (indicated when vsc8601 device register bit 1.2 reads 0), the inline power should be disabled to the inline powered device external to the phy. the vsc8601 phy disables its normal auto-negotiation process and re-enables its inline powered device detection mode. 3.10 actiphy power management in addition to the ieee-specified power-down control bit (device register bit 0.11), the device also includes an actiphy? power ma nagement mode for each phy. this mode enables support for power-sensitive applications such as laptop computers with wake-on-lan? capability. it utilizes a signal-detect function that monitors the media interface for the presence of a link to dete rmine when to automatically power-down the phy. the phy ?wakes up? at a programmable interval and attempts to ?wake up? the link partner phy by sending a burst of flp over copper media. the actiphy power management mode in th e vsc8601 device can be enabled during normal operation at any time by setting register bit 23.5 to 1. there are three operating states possible when actiphy mode is enabled: ? low-power state ?lp wake-up state ? normal operating state (link-up state) the vsc8601 device switches between the lo w-power state and lp wake-up state every two seconds until signal energy is detected on the media interface pins. when signal energy is detected, the phy enters the normal operating state. if the phy is in its normal operating state and the link fails, th e phy returns to the low-power state after the link status time-out timer has expired. after reset, the phy enters the low-power state. when auto-negotiation is enabled in the ph y, the actiphy state machine operates as described. if auto-negotiation is disabled and the link is forced to 10bt or 100btx modes while the phy is in its low-power stat e, the phy continues to transition between the low-power and lp wake-up states until sign al energy is detected on the media pins. at that time, the phy transitions to the normal operating state and stays in that state even when the link is dropped. if auto-negot iation is disabled while the phy is in the normal operation state, the phy stays in that state when the link is dropped and does not transition back to the low-power state.
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 24 the following illustration shows the relationship between actiphy states and timers. figure 7. actiphy state 3.10.1 low-power state in the low-power state, all major digital blocks are powered down. however, the following functionality is provided: ? smi interface (mdc, mdio, mdint) ?clkout in this state, the phy monitors the media interface pins for signal energy. the phy comes out of low-power state and transitions to the normal operating state when signal energy is detected on the media. this happens when the phy is connected to one of the following: ? auto-negotiation capable link partner ? auto-negotiation incapable (blink/forced) link partner (100base-tx or 10base-t) ? another phy in actiphy lp wake-up state in the absence of signal energy on the media pins, the phy transitions from the low-power state to the lp wake-up state peri odically based on the programmable sleep timer (register bits 20e.14:13). the actual sleep time duration is randomized from ?80 ms to +60 ms to avoid two linked phys in actiphy mode entering a lock-up state during operation. low-power state lp wake-up state normal operation flp burst signal sent sleep timer expires timeout timer expires and auto-negotiation enabled signal energy detected on media
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 25 3.10.2 link partner wake-up state in this state, the phy attempts to wake up the link partner. flp bursts are sent on alternating pairs a and b of the cat5 media for a duration of two seconds. in this state, the following functionality is provided: ? smi interface (mdc, mdio, mdint) ?clkout after sending signal energy on the relevant media, the phy returns to the low-power state. 3.10.3 normal operating state in this state, the phy establishes a link with a link partner. when the media is unplugged or the link partner is powered down, the phy waits for the duration of the programmable link status time-out timer, which is set using register bit 28.7 and bit 28.2. it then enters the low-power state. 3.11 serial management interface the vsc8601 device includes an ieee 802.3-compliant serial management interface (smi) that is affected by use of its mdc and mdio pins. the smi provides access to device control and status registers. the register set that controls the smi consists of 32 16-bit registers, including all required i eee-specified registers. also, there are additional pages of registers accessible by means of device register 31. for more information, see ?extended page registers,? page 55. the smi is a synchronous serial interface with bidirectional data on the mdio pin that is clocked on the rising edge of the mdc pin. the interface can be clocked at a rate from 0 mhz to 25 mhz, depending upon the total load on mdio. an external, 2 k pull-up resistor is required on the mdio pin. 3.11.1 smi frames data is transferred over the smi using 32-bit frames with an optional and arbitrary length preamble. the following illustrations show the smi frame format for the read operation and write operation.
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 26 figure 8. smi read frame figure 9. smi write frame the following provides additional informat ion about the terms used in figure 8 and figure 9. idle during idle, the mdio node goes to a high-impedance state. this allows an external pull-up resistor to pull the mdio node up to a logical 1 state. because the idle mode should not contain any transitions on mdio, the number of bits is undefined during idle. preamble by default, preambles are not expected nor required. the preamble is a string of ones. if it exists, the preamble must be at least one bit; otherwise, it may be of an arbitrary length. start of frame (sfd) a pattern of 01 indicates the star t of frame. if the pattern is not 01, all following bits are ignored unt il the next preamble pattern is detected. read or write opcode a pattern of 10 indicates a read. a pattern of 01 indicates a write. if these bits are not either 01 or 10 , all following bits are ignored until the next preamble pattern is detected. phy address the vsc8601 responds to a message frame only when the received phy address matches its physical address. the physical address is five bits long (4:0). the bits are set by the cmode pins. register address the next five bits are the register address. turn-around the two bits used to avoid signal contention when a read operation is performed on the mdio are called the turn-a round (ta) bits. during read operations, the vsc8601 device drives the second ta bit, which is a logical 0. data the 16-bits read from or written to the device are considered the data or data stream. when data is read from a phy, it is valid at the output from one rising edge of mdc mdio preamble (optional) sfd 1 z10 read 1 0 phy address a4 a3 a2 a1 a0 r4 r3 r2 r1 r0 register address to phy z0 ta register data from phy d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 z z idle idle z station manager drives mdio phy drives mdio mdc mdio preamble (optional) sfd 1 z10 write 01 phy address a4 a3 a2 a1 a0 r4 r3 r2 r1 r0 register address to phy 10 ta register data from phy d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 z z idle idle z station manager drives mdio (phy tristates mdio during entire sequence)
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 27 mdc to the next rising edge of mdc. when da ta is being written to the phy, it must be valid around the rising edge of mdc. idle the sequence is repeated. 3.11.2 smi interrupts the smi also includes an output interrupt signal, mdint, for signaling the station manager when certain events occur in the phy. the mdint pin can be configured for open-d rain (active-low) by tying the pin to a pull-up resistor and to vddio. the following illustration shows this configuration. figure 10. mdint configured as an open-d rain (active-low) pin alternatively, each mdint pin can be configured for open-source (active-high) by tying the pin to a pull-down resistor and to vss. the following illustration shows this configuration. figure 11. mdint configured as an open-source (active-high) pin when a phy generates an interrupt, the mdin t pin is asserted (driven high or low, depending on resistor connection) if the interrupt pin enable bit (mii register 25.15) is set. mdint (to station manager) interrupt pin enable (mii register 25.15) interrupt pin status (mii register 26.15) external pull-up at station manager for open-drain (active low mode) vddio mdint mdint (to station manager) interrupt pin enable (mii register 25.15) interrupt pin status (mii register 26.15) external pull-down at station manager for open source (active-high mode) vddio mdint
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 28 3.12 led interface the vsc8601 device drives up to three leds directly. all led outputs are active-low and are driven using 3.3 v from the vdd33 power supply. when active, the pins are mainly used to sink current of the cathode si de of an led, but the pins can also supply source power to the anode portion of leds wh en they are not in the active state. this allows for two led pins to be used to drive a multi-status, bi-colored led. 3.12.1 simple or enhanced led method the vsc8601 provides two methods for controlling its leds: simple or enhanced. the simple led method is backward-compatible to the led control found in prior vitesse ethernet phy devices. the simple led method eases software backward compatibility for customers switching to the vsc8601. the simple led method is controlled by mii register 27 and is enabled by default. for added flexibility, the vsc8601 led can be controlled using the enhanced led method. the enhanced led method is enabled by setting mii register 17e.4 = 1. when enabled, then the leds are controlled by mii registers 16e and 17e. in this method, the mii register 27 settings are ignored. simple led method when mii register 17e.4 = 0, the leds are controlled by the simple led method. this led method is enab led on power-up and is controlled by mii register 27. in this method, mii register 27 controls the leds. for more information, see ?led control,? page 52. enhanced led method when mii register 17e.4 = 1, the leds are controlled by the enhanced led method. in this method, mii register 16e and 17e control the leds. for more information, see ?enhanced led method select,? page 56 and ?enhanced led behavior,? page 57. 3.12.2 led modes if you are using the enhanced led method , there are several led modes available. they are found in mii register 16e. each le d pin can be configured to display different status information. set the led mode either by using register 16e or with the cmode pin setting. the following table summarizes the led functions. note the modes listed in the following table are equivalent to the setting used in register 16e to configure each led pin. for the led states listed, 1 = pin held high (de-asserted), 0 = pin held low (asserted), and blink/pulse-stretch is dependent on the led behavior setting in register 17e. table 3. led mode and function summary mode function name led state and description 0 link/activity 1 = no link in any speed on any media interface. 0 = valid link at any speed on any media interface. blink or pulse-stretch = valid link at any speed on any media interface and with activity present. 1 link1000/activity 1 = no link in 1000base-t. 0 = valid 1000base-t link. blink or pulse-stretch = valid 1000base-t link with activity present.
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 29 2 link100/activity 1 = no link in 100base-tx. 0 = valid 100base-tx link. blink or pulse-stretch = valid 100base-tx link with activity present. 3 link10/activity 1 = no link in 10base-t. 0 = valid 10base-t link. blink or pulse-stretch = valid 10base -t link with activity present. 4 link100/1000/activity 1 = no link in 100base-tx or 1000base-t. 0 = valid 100base-tx or 1000base-t link. blink or pulse-stretch = valid 100base-tx or 1000base-t link with activity present. 5 link10/1000/activity 1 = no link in 10base-t or 1000base-t. 0 = valid 10base-t or 1000baset-t link. blink or pulse-stretch = valid 10base-t or 1000base-t link with activity present. 6 link10/100/activity 1 = no link in 10base-t or 100base-tx. 0 = valid 10base-t or 100base-tx link. blink or pulse-stretch = valid 10base-t or 100base-tx link with activity present. 7 reserved 8 duplex/collision 1 = link established in half-duplex mode, or no link established. 0 = link established in full-duplex mode. blink or pulse-stretch = link established in half-duplex mode but collisions are present. 9 collision 1 = no collision detected. blink or pulse-stretch = collision detected. 10 activity 1 = no activity present. blink or pulse-stretch = activity present (becomes tx activity present if register bit 30.14 is set to 1). 11 reserved 12 auto-negotiation fault 1 = no auto-negotiation fault present. 0 = auto-negotiation fault occurred. 13 reserved 14 force led off 1 = de-asserts the led. 15 force led on 0 = asserts the led. table 3. led mode and function summary (continued) mode function name led state and description
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 30 3.12.3 led behavior several led behaviors can be programmed into the vsc8601 device. use the settings in register 17e to program led beha vior, which includes the following: led combine enables an led to display status for a combination of primary and secondary modes. this can be enabled or disabled for each led pin. for example, a copper link running in 1000base-t mode and ac tivity present can be displayed with one led by configuring an led pi n to link1000/activity mode. the led asserts when linked to a 1000base-t partner and also blinks or pulse-stretches when activity is either transmitted by the phy or received by th e link partner. the combine feature when disabled only allows status of the primary function selected. in this example, only link1000 asserts the led, and the secondary mode, activity, does not display if the combine feature is disabled. led blink or pulse-stretch this behavior is used for activity and collision indication. this can be uniquely configured for each led pin. activity and collision events can occur randomly and intermittently throughout the lin k-up period. for activity or collision to be visually seen, these two modes are provided. blink is a 50% duty cycle oscillation of asserting and de-asserting an led pin. pulse-st retch guarantees that an led is asserted and de-asserted for a specific period of time when activity is either present or not present. these rates can also be configured using a register setting. rate of led blink or pulse-stretch this controls the led blink rate or pulse-stretch length when blink/pulse-stretch is enable d on an led pin. th e blink rate, which alternates between a high and low voltage le vel at a 50% duty cycle, can be set to 2.5 hz, 5 hz, 10 hz, or 20 hz. for pulse-stretch, this can be set to 50 ms, 100 ms, 200 ms, or 400 ms. led pulsing enable to provide additional power savings, the leds (when asserted) can be pulsed at 5 khz, 20% duty cycle. 3.13 testing features the vsc8601 device includes several testing features designed to make it easier to perform system-level debugging and in-system production testing. this section describes the available features. 3.13.1 ethernet packet generator (epg) the device epg can be used at each of the 10/100/1000base-t speed settings to isolate problems between the mac and the vsc8601 device, or between a locally connected phy and its remote link partner. en abling the epg feature effectively disables all mac interface transmit pins and selects the epg as the source for all data transmitted onto the twisted pair interface. note the epg is intended for use with laboratory or in-system testing equipment only. do not use the epg testing feature when the vsc8601 device is connected to a live network. to enable the vsc8601 device epg feature, set the device register bit 29e.15 to 1. when the epg is enabled, packet loss occurs during transmission of packets from the mac to the phy. however, the phy receive ou tput pins to the mac are still active when
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 31 the epg is enabled. if it is necessary to disable the mac receive pins as well, set register bit 0.10 to 1. when the device register bit 29e.14 is set to 1, the phy begins transmitting ethernet packets based on the settings in registers 29e and 30e. these registers set: ? source and destination addresses for each packet ?packet size ?inter-packet gap ? fcs state ? transmit duration ? payload pattern if register bit 29e.13 is set to 0, register bit 29e.14 is cleared automatically after 30,000,000 packets are transmitted. 3.13.2 crc counters two separate cyclical redundancy checking (crc) counters are available in the vsc8601 device. there is a 14-bit crc good counter available in register bits 18e.13:0 and a separate 8-bit crc error counter available in register bits 23e.7:0. the device crc counters operate in 10/100/1000base-t testing as follows: ? after receiving a packet on the media in terface, register bit 18e.15 is set and cleared after being read. the packet then is counted by either the crc good counter or the crc error counter. both crc counters are also automatically cleared when read. ? the crc good counter?s highest value is 9,999 packets. upon receiving the next packet, the counter clears and continues to count additional packets beyond that value. the crc error counter saturates when it reaches its maximum counter limit of 255 packets. 3.13.3 far-end loopback the far-end loopback testing feature is enab led by setting register bit 27e.10 to 1. when enabled, it forces incoming data from a link partner on the current media interface to be retransmitted back to the link partner on the media interface as shown in the following illustration. in addition, the incoming data also appears on the receive data pins of the mac interface. data pres ent on the transmit data pins of the mac interface is ignored when using this testing feature.
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 32 figure 12. far-end loopback 3.13.4 near-end loopback when the near-end loopback testing feature is enabled (by setting the device register bit 0.14 to 1), data on the transmit data pi ns (txd) is looped ba ck onto the device received data pins (rxd) as illustrated in the following illustration. when using this testing feature, no data is transmitted over the network. figure 13. near-end loopback 3.13.5 connector loopback the connector loopback testing feature allows for the twisted pair interface to be looped back externally. when using this feature, the phy must be connected to a loopback connector or a loopback cable. pair a should be connected to pair b and pair c to pair d, as shown in the following illustration . the connector loopback feature functions at all available interface speeds. figure 14. connector loopback when using the connector loopback testing fe ature, the device auto-negotiation, speed, and duplex configuration is set using device registers 0, 4, and 9. for 1000base-t link partner simpliphy mac rx tx rxd txd cat5 link partner simpliphy mac rx tx rxd txd cat5 simpliphy mac rxd txd cat5 a b c d
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 33 connector loopback, only the following additional writes are required. execute the additional writes in the following order: 1. enable the 1000base-t connector loopback. set register bit 24.0 to 1. 2. disable the pair swap correction. set register bit 18.5 to 1. 3.13.6 veriphy cable diagnostics the vsc8601 device includes a comprehensive suite of cable diagnostic functions that are available using smi reads and writes. th ese functions enable a variety of cable operating conditions and status to be accessed and checked. the veriphy suite has the ability to identify the cable length and operat ing conditions and to isolate a variety of common faults that can occur on the cat5 twisted pair cabling. for more information, refer to the phy api software and programmers guide on the vitesse web site at www.vitesse.com. note if a link is established on the twisted pair interface in 1000base-t mode, veriphy can run without disrupting the link or any data transfer. however, if a link is established in 100base-tx or 10base-t, ve riphy causes the link to drop while the diagnostics are running. after the diagno stics are finished, the link is then re-established. the following diagnostic functions are part of the veriphy suite: ? detection of coupling between cable pairs ? detection of cable pair termination ? determination of cable length coupling between cable pairs shorted wires, improper termination, or high crosstalk resulting from an incorrect wire map can cause error conditions, such as anomalous coupling between cable pairs. thes e conditions can all prevent the device from establishing a link at any speed. cable pair termination proper termination of cat5 cable requires 100- differential impedance between the positive and negative cable terminals. the ieee standard 802.3 allows for a termination of as high as 115 or as low as 85 . if the termination falls outside of this range, it is reported by the veriphy diagnostics as an anomalous termination. the diagnostics can also determ ine the presence of an open or shorted cable pair. cable length when the cat5 cable in an installation is properly terminated, veriphy reports the approximate cable length in meters. 3.13.7 ieee 1149.1 jtag boundary scan the vsc8601 device supports the test access port (tap) and boundary-scan architecture described in the ieee standard 1149.1. the device includes an ieee 1149.1-compliant test interface, often referred to as a ?jtag tap interface.? the jtag boundary-scan logic on the vsc8601 device, accessed using its tap interface, consists of a boundary-scan register and other logic control blocks. the tap controller
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 34 includes all ieee-required signals (tms, tck, tdi, and tdo), in addition to the optional asynchronous reset signal ntrst. the following illustration shows the tap and boundary-scan architecture. figure 15. test access port an d boundary-scan architecture after a tap reset, the device identification register is serially connected between tdi and tdo by default. the tap instruction regist er is loaded either from a shift register (when a new instruction is shifted in) or, if there is no new instruction in the shift register, a default value of 0110 (idcode) is loaded. using this method, there is always a valid code in the instruction register, an d the problem of toggling instruction bits during a shift is avoided. unused code s are mapped to the bypass instruction. 3.13.8 jtag instruction codes the vsc8601 device supports the following instruction codes: extest allows testing of off-chip circuitry and board-level interconnections by sampling input pins and loading data onto output pins. outputs are driven by the contents of the boundary-scan cells, which have to be updated with valid values (with the preload instruction) prior to the extest instruction. boundary-scan register device identification register bypass register instruction register, instruction decode, control test access port controller ntrst tms tdi tck select control tdoenable control mux, dff tdo
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 35 sample/preload allows a snapshot of inputs and outputs during normal system operation to be taken and examined. it also allows data values to be loaded into the boundary-scan cells prior to the selection of other boundary-scan test instructions. idcode provides the version number (bits 31:28), part number (bits 27:12), and the manufacturer identity (bits 11:1) to be serially read from the device. the following table provides information about the meaning of idcode binary values stored in the device jtag registers. clamp allows the state of the signals driven from the component pins to be determined from the boundary-scan register wh ile the bypass register is selected as the serial path between tdi and tdo. while the clamp instruction is selected, the signals driven from the component pins do not change. highz places the component in a state in which all of its system logic outputs are placed in a high impedance state. in this state, an in-circuit test system may drive signals onto the connections normally driven by a component output without incurring a risk of damage to the component. this makes it possible to use a board where not all of the components are compatible with the ieee 1149.1 standard. bypass the bypass register contains a single shift-register stage and is used to provide a minimum-length serial path (one tck clock period) between tdi and tdo to bypass the device when no test operation is required. the following table provides more information about the location and ieee compliance of the jtag instruction codes used in the vsc8601. table 4. jtag device identification register description description device version number model number manufacturing identity lsb bit field 31 through 28 27 through 12 11 through 1 0 binary value 0001 1000 0110 0000 0001 000 0111 0100 1 table 5. jtag interface instruction codes instruction code selected register register width ieee 1149.1 specification extest 0000 boundary-scan 45 mandatory sample/preload 0001 boundary-scan 45 mandatory idcode 0110 device identification 32 optional clamp 0010 bypass register 1 optional highz 0011 bypass register 1 optional bypass 1111 bypass register 1 mandatory reserved 0100, 0101, 0111, 1000-1110
vsc8601 datasheet functional descriptions revision 4.1 september 2009 page 36 3.13.9 boundary-scan re gister cell order all inputs and outputs are observed in the boundary-scan register cells. all outputs are additionally driven by the contents of boundary-scan register cells. bidirectional pins have all three related boundary-scan regi ster cells: input, output, and control. the complete boundary-scan cell order is availa ble as a bsdl file format on the vitesse web site at www.vitesse.com.
vsc8601 datasheet configuration revision 4.1 september 2009 page 37 4 configuration the vsc8601 device can be configured using three different methods: ? setting internal memory register s using the management interface. ? setting a combination of cmode pins and registers. ? loading a configuration into an external ee prom and connecting that device so that it writes configuration information at system startup. 4.1 registers this section provides information about how to configure the vsc8601 device using its internal memory registers and the management interface. for information about configuring the device us ing the cmode pins, see ?cmode,? page 64. for information about setting up an external eeprom to perform startup configuration, see ?eeprom,? page 66. the following illustration shows the relationsh ip between the device registers and their address spaces. figure 16. register space diagram ieee 802.3 standard registers extended page registers main registers 0x0000 0x0001 31 0 1 2 3 . . . . . . . . 15 16 17 18 19 . . . . . . . . 30 16e 17e 18e 19e . . . . . . . . 30e
vsc8601 datasheet configuration revision 4.1 september 2009 page 38 4.1.1 reserved registers for main registers 16 through 31 and extended page registers 16e through 30e, any bits marked as ?reserved? should be processed as read only and their states as undefined. 4.1.2 reserved bits in writing to registers with reserved bits, use a ?read-modify-then-write? technique, where the entire register is read but only th e intended bits to be changed are modified. reserved bits cannot be changed and their read state cannot be considered static or unchanging. 4.2 ieee standard and main registers in the vsc8601 device, the standard registers? page space consists of the ieee standard registers and the vitesse standard registers. the following table lists the names of the registers associated with the addresses as dictated by the ieee standard. the following table lists the names of the registers in the main page space of the device. these registers are accessible only when register address 31 is set to 0x0000. table 6. ieee 802.3 standard registers register address register name 0mode control 1mode status 2 phy identifier 1 3 phy identifier 2 4 auto-negotiation advertisement 5 auto-negotiation link partner ability 6 auto-negotiation expansion 7 auto-negotiation next-page transmit 8 auto-negotiation link pa rtner next-page receive 9 1000base-t control 10 1000base-t status 11 reserved 12 reserved 13 reserved 14 reserved 15 1000base-t status extension 1 table 7. main registers register address register name 16 100base-tx status extension 17 1000base-t status extension 2
vsc8601 datasheet configuration revision 4.1 september 2009 page 39 4.2.1 mode control the device register at memory address 0. 00.15:0 controls several aspects of vsc8601 functionality. the following table lists the available bit settings in this register and what they control. 18 bypass control 19 receive error counter 20 false carrier sense counter 21 disconnect counter 22 extended control and status 23 extended phy control 1 24 extended phy control 2 25 interrupt mask 26 interrupt status 27 led control 28 auxiliary control and status 29 delay skew status 30 reserved 31 extended register page access table 8. mode control, address 0 (0x00) bit name access description default 15 software reset r/w this is a self -clearing bit that restores all serial management inte rface (smi) registers to their default state, except for sticky and super sticky bits. 1 = reset asserted. 0 = reset de-asserted. you must wait 4 s after setting this bit to initiate another smi register access. 0 14 loopback r/w 1 = loopback enabled. 0 = loopback disabled. when loop back is enabled, the device functions at the curre nt speed setting and with the current duplex mode setting (bit 8 of this register). 0 13, 6 forced speed selection r/w lsb = bit 13, msb = bit 6. 00 = 10 mbps. 01 = 100 mbps. 10 = 1000 mbps. 11 = reserved. 10 12 auto-negotiation enable r/w 1 = auto-negotiation enabled. 0 = auto-negotiation disabled. 1 table 7. main registers (continued) register address register name
vsc8601 datasheet configuration revision 4.1 september 2009 page 40 4.2.2 mode status the register at 1.01.15:0 in the device ma in registers space displays the currently enabled mode setting. the following table lists possible readouts of this register. 11 power-down r/w 1 = power-down enabled. if power-down is enabled, the rgmii?s in-band signaling is disabled. when this bit is set, rgmii in-ban d signaling does not function. 0 10 isolate r/w 1 = disable mac interface outputs and ignore mac interface inputs. 0 9restart auto-negotiation r/w this is a self-clearing bit. 1 = restart auto-negotiation on media interface. 0 8 duplex r/w 1 = full-duplex. 0 = half-duplex. 0 7 collision test enable r/w 1 = collision test enabled. 0 6 msb for speed selection r/w see bit 13 above. 1 5:0 reserved 000000 table 9. mode status, address 1 (0x01) bit name access description default 15 100base-t4 capability ro 1 = 100base-t4 capable. 0 14 100base-x fdx capability ro 1 = 100base-x fdx capable. 1 13 100base-x hdx capability ro 1 = 100base-x ddx capable. 1 12 10base-t fdx capability ro 1 = 10base-t fdx capable. 1 11 10base-t hdx capability ro 1 = 10base-t hdx capable. 1 10 100base-t2 fdx capability ro 1 = 100base-t2 fdx capable. 0 9 100base-t2 hdx capability ro 1 = 100base-t2 hdx capable. 0 8 extended status enable ro 1 = extended status information present in register 15. 1 7 reserved ro 0 6preamble suppression capability ro 1 = mf preamble may be suppressed. 0 = mf always required. 1 5 auto-negotiation complete ro 1 = auto-negotiation complete. 0 table 8. mode control, address 0 (0x00) (continued) bit name access description default
vsc8601 datasheet configuration revision 4.1 september 2009 page 41 4.2.3 device identification all 16 bits in both register 2 and register 3 in the vsc8601 device are used to provide information associated with aspects of the de vice identification. the following tables list the possible readouts. 4.2.4 auto-negotiation advertisement the bits in address 4 in the main register s space control the vsc8601 device ability to notify other devices of the status of its auto-negotiation feature. the following table lists the available settings and readouts. 4 remote fault ro this bit latches high. 1 = far-end fault detected. 0 3 auto-negotiation capability ro 1 = auto-negotiation capable. 1 2 link status ro this bit latches low. 1 = link is up. 0 1 jabber detect ro this bit latches high. 1 = jabber condition detected. 0 0 extended capability ro 1 = ex tended register capable. 1 table 10. identifier 1, address 2 (0x02) bit name access description default 15:0 organizationally unique identifier (oui) ro oui most significant bits (3:18) 0x0007 table 11. identifier 2, address 3 (0x03) bit name access description default 15:10 oui ro oui least significant bits (19:24) 0x0001 9:4 vitesse model number ro vsc8601 000010 3:0 device revision number ro 0001 table 12. device auto-negotiation advertisement, address 4 (0x04) bit name access description default 15 next page transmission request r/w 1 = request enabled 0 14 reserved ro 0 13 transmit remote fault r/w 1 = enabled 0 table 9. mode status, address 1 (0x01) (continued) bit name access description default
vsc8601 datasheet configuration revision 4.1 september 2009 page 42 4.2.5 link partner auto-n egotiation capability the bits in main register 5 enable you to determine if the cat5 link partner (lp) used with the vsc8601 device is compatible with the auto-negotiation functionality. 12 reserved technologies r/w 0 11 advertise asymmetric pause r/w 1 = advertises as ymmetric pause cmode 10 advertise symmetric pause r/w 1 = advertises symmetric pause cmode 9advertise 100base-t4 r/w 1 = advertises 100base-t4 0 8advertise 100base-tx fdx r/w 1 = advertise 100base-tx fdx cmode 7advertise 100base-tx hdx r/w 1 = advertises 100base-tx hdx cmode 6advertise 10base-t fdx r/w 1 = advertises 10base-t fdx cmode 5advertise 10base-t hdx r/w 1 = advertises 10base-t hdx cmode 4:0 advertise selector r/w 00001 table 13. auto-negotiation link partner ability, address 5 (0x05) bit name access description default 15 lp next page transmission request ro 1 = requested 0 14 lp acknowledge ro 1 = acknowledge 0 13 lp remote fault ro 1 = remote fault 0 12 reserved ro 0 11 lp advertise asymmetric pause ro 1 = capable of asymmetric pause 0 10 lp advertise symmetric pause ro 1 = capable of symmetric pause 0 9lp advertise 100base-t4 ro 1 = capable of 100base-t4 0 8lp advertise 100base-tx fdx ro 1 = capable of 100base-tx fdx 0 7lp advertise 100base-tx hdx ro 1 = capable of 100base-tx hdx 0 6lp advertise 10base-t fdx ro 1 = capable of 10base-t fdx 0 5lp advertise 10base-t hdx ro 1 = capable of 10base-t hdx 0 4:0 lp advertise selector ro 00000 table 12. device auto-negotiation advertisement, address 4 (0x04) bit name access description default
vsc8601 datasheet configuration revision 4.1 september 2009 page 43 4.2.6 auto-negotiation expansion the bits in main register 6 work together with those in register 5 to indicate the status of the lp auto-negotiation. the following ta ble lists the available settings and readouts. 4.2.7 transmit auto-negotiation next page the settings in register 7 in the main registers space provide information about the number of pages in an auto-negotiation se quence. the following table lists the settings available. table 14. auto-negotiation expansion, address 6 (0x06) bit name access description default 15:5 reserved ro 00000000000 4 parallel detection fault ro this bit latches high. 1 = parallel detection fault. 0 3 lp next page capable ro 1 = lp is next page capable. 0 2 local phy next page capable ro 1 = local phy is next page capable. 1 1 page received ro this bit latches low. 1 = new page has been received. 0 0lp is auto-negotiation capable ro 1 = lp is capable of auto-negotiation. 0 table 15. auto-negotiation next page transmit, address 7 (0x07) bit name access description default 15 next page r/w 1 = more pages follow 0 14 reserved ro 0 13 message page r/w 1 = message page 0 = unformatted page 1 12 acknowledge 2 r/w 1 = co mplies with request 0 = cannot comply with request 0 11 toggle ro 1 = previous transmitted lcw = 0 0 = previous transmitted lcw = 1 0 10:0 message/unformatted code r/w 00000000001
vsc8601 datasheet configuration revision 4.1 september 2009 page 44 4.2.8 auto-negotiation link partner next page receive the bits in register 8 of the main register space work together with register 7 to determine certain aspects of the lp auto-n egotiation. the following table lists the possible readouts. 4.2.9 1000base-t control the vsc8601 device?s 1000base-t functionality is controlled by the bits in register 9 of the main register space. the following table lists the settings and readouts available. note transmitter test mode (bits 15:13) operates in the manner described in ieee standard 802.3, section 40.6.1.1.2. table 16. auto-negotiation lp next page receive, address 8 (0x08) bit name access description default 15 lp next page ro 1 = more pages follow 0 14 acknowledge ro 1 = lp acknowledge 0 13 lp message page ro 1 = message page 0 = unformatted page 0 12 lp acknowledge 2 ro 1 = lp complies with request 0 11 lp toggle ro 1 = previous transmitted lcw = 0 0 = previous transmitted lcw = 1 0 10:0 lp message / unformatted code ro 00000000000 table 17. 1000base-t control, address 9 (0x09) bit name access desc ription default 15:13 transmitter test mode r/w 000 = normal. 001 = mode 1: transmit waveform test. 010 = mode 2: transmit jitter test as master. 011 = mode 3: transmit jitter test as slave. 100 = mode 4: transmitter distortion test. 101 to 111 = reserved: operation not defined. 000 12 master/slave manual configuration r/w 1 = master/slave manual configuration enabled. 0 11 master/slave value r/w this register is only vali d when bit 9.12 is set to 1. 1 = configure phy as master during negotiation. 0 = configure phy as slave during negotiation. 0 10 port type r/w 1 = multi-port device. 0 = single-port device. 0 9 1000base-t fdx capability r/w 1 = phy is 1000base-t fdx capable. cmode 8 1000base-t hdx capability r/w 1 = phy is 1000base-t hdx capable. cmode 7:0 reserved r/w 0x00
vsc8601 datasheet configuration revision 4.1 september 2009 page 45 4.2.10 1000base-t status the bits in register 10 of the main register space allow you to read the status of the 1000base-t communications enabled in the device. the following table lists these readouts. 4.2.11 main registers reserved addresses in the vsc8601 device main registers page space, registers 11 through 15 (0x0b through 0x0e) are reserved. 4.2.12 1000base-t status extension 1 register 15 provides additional information about the operation of the device 1000base-t communications. the following table lists the readouts available. table 18. 1000base-t status, address 10 (0x0a) bit name access description default 15 master/slave configuration fault ro this bit latches high. 1 = master/slave configuration fault detected. 0 = no master/slave configuration fault detected. 0 14 master/slave configuration resolution ro 1 = local phy configuration resolved to master. 0 = local phy configuration resolved to slave. 1 13 local receiver status ro 1 = local receiver okay. 0 12 remote receiver status ro 1 = remote receiver ok. 0 11 lp 1000base-t fdx capability ro 1 = lp 1000base-t fdx capable. 0 10 lp 1000base-t hdx capability ro 1 = lp 1000base-t hdx capable. 0 9:8 reserved ro 00 7:0 idle error count ro this is a self-clearing bit. 0x00 table 19. 1000base-t status extension 1, address 15 (0x0f) bit name access description default 15 1000base-x fdx capability ro 1 = phy is 1000base-x fdx capable 0 14 1000base-x hdx capability ro 1 = phy is 1000base-x hdx capable 0 13 1000base-t fdx capability ro 1 = phy is 1000base-t fdx capable 1 12 1000base-t hdx capability ro 1 = phy is 1000base-t hdx capable 1 11:0 reserved ro 0x000
vsc8601 datasheet configuration revision 4.1 september 2009 page 46 4.2.13 100base-tx status extension register 16 in the main registers page spac e of the vsc8601 device provides additional information about the status of the device?s 100base-tx operation. 4.2.14 1000base-t status extension 2 the second status extension register is at address 17 in the device main registers space. it provides information about another set of parameters associated with 1000base-t communications. for information ab out the first status extension register, see ta b l e 2 0 , page 46. the following table lists the settings available. table 20. 100base-tx status extension, address 16 (0x10) bit name access description default 15 100base-tx descrambler ro 1 = descrambler locked. 0 14 100base-tx lock error ro this is a self-clearing bit. 1 = lock error detected. 0 13 100base-tx disconnect state ro this is a self-clearing bit. 1 = phy 100base-tx link disconnect detected. 0 12 100base-tx current link status ro 1 = phy 100base-tx link active. 0 11 100base-tx receive error ro this is a self-clearing bit. 1 = receive error detected. 0 10 100base-tx transmit error ro this is a self-clearing bit. 1 = transmit error detected. 0 9 100base-tx ssd error ro this is a self-clearing bit. 1 = start-of-stream delimiter error detected. 0 8 100base-tx esd error ro this is a self-clearing bit. 1 = end-of-stream delimiter error detected. 0 7:0 reserved ro table 21. 1000base-t status extension 2, address 17 (0x11) bit name access description default 15 1000base-t descrambler ro 1 = descrambler locked. 0 14 1000base-t lock error ro this is a self-clearing bit. 1 = lock error detected. 0 13 1000base-t disconnect state ro this is a self-clearing bit. 1 = phy 1000base-t link disconnect detected. 0 12 1000base-t current link status ro 1 = phy 1000base-t link active. 0 11 1000base-t receive error ro this is a self-clearing bit. 1 = receive error detected. 0 10 1000base-t transmit error ro this is a self-clearing bit. 1 = transmit error detected. 0
vsc8601 datasheet configuration revision 4.1 september 2009 page 47 4.2.15 bypass control the bits in the bypass control register in the vsc8601 device control aspects of functionality in effect when the device is disabled so that traffic can bypass it in your design. the following table lists the settings available. 9 1000base-t ssd error ro this is a self-clearing bit. 1 = start-of-stream delimiter error detected. 0 8 1000base-t esd error ro this is a self-clearing bit. 1 = end-of-stream delimiter error detected. 0 7 1000base-t carrier extension error ro this is a self-clearing bit. 1 = carrier extensio n error detected. 0 6 non-compliant bcm5400 detected ro 1 = non-compliant bcm5400 detected. 0 5 mdi crossover error ro 1 = md i crossover error detected. 0 4:0 reserved ro table 22. bypass contro l, address 18 (0x12) bit name access description default 15 transmit disable r/w 1 = phy transmitter disabled. 0 14:9 reserved ro 8 1000base-t transmitter test clock r/w 1 = enabled. 0 7 force non-compliant bcm5400 detection r/w this is a sticky bit. 1 = force non-compliant bcm5400 detection. 0 6 non-compliant bcm5400 detection disable r/w this is a sticky bit. 1 = non-compliant bcm5400 detection disable. 1 5 disable pair swap correction r/w this is a sticky bit. 1 = disable the automatic pair swap correction. 0 4 disable polarity correction r/w this is a sticky bit. 1 = disable polarity inversion correction on each subchannel. 0 3 parallel detect control r/w this is a sticky bit. 1 = do not ignore advertised ability. 0 = ignore advertised ability. 1 2 reserved ro 1 disable automatic 1000base-t next page exchange r/w this is a sticky bit. 1 = disable automatic 1000base-t next page exchanges. 0 0clkout output enable r/w this is a sticky bit. 1 = enable clock output pin. cmode table 21. 1000base-t status extension 2, address 17 (0x11) (continued) bit name access description default
vsc8601 datasheet configuration revision 4.1 september 2009 page 48 note if bit 1 is set to 1 in this register, automatic exchange of next pages is disabled, and control is returned to the user through the smi after the base page is exchanged. the user then must send the correct sequence of next pages to the link partner, determine the common capabilities, and force the device into the correct configuration following the successful exchange of pages. 4.2.16 receive error counter the following table lists the readouts you can expect. 4.2.17 false carrier sense counter the following table lists the readouts you can expect. table 23. receive error counter, address 19 (0x13) bit name access description default 15:8 reserved ro 00000000 7:0 receive error counter ro this is a self-clearing bit. counts the number of non-collision packets with receive errors since last read. each time the phy detects a non-collision packet containing at least one error, these bits are incremented. the counter stops counting at 0ffh. this register is clea red only when read, or upon either a hardware or software reset. these bits are valid only in 100base-tx and 1000base-t modes. 00000000 table 24. false carrier sense counter, address 20 (0x14) bit name access description default 15:8 reserved ro 00000000 7:0 false carrier sense counter ro this is a self-clearing bit. counts the number of false carrier events since last read. the phy increments these bits each time it detects a false carrier on the receive input. the counter stops counting at 0ffh. this register is clea red only when read, or upon either a hardware or software reset. these bits are valid only in 100base-tx and 1000base-t modes. 00000000
vsc8601 datasheet configuration revision 4.1 september 2009 page 49 4.2.18 disconnect counter the following table lists the readouts you can expect. 4.2.19 extended control and status the bits in register 22 provide additional device control and readouts. the following table lists the settings available. the following information applies to the extended control and status bits: ? when bit 15 is set, the link integrity st ate machine is bypassed and the phy is forced into a link pass status. table 25. disconnect counter, address 21 (0x15) bit name access description default 15:8 reserved ro 00000000 7:0 disconnect counter ro this is a self-clearing bit. counts the number of non-collision packets with receive e rrors after the last read. the phy increments these bits each time the carrier integrity monitor (cim) enters the link unstable state. the counter stops counting at 0ffh. this register is cleared only when read or upon a hardware or software reset. 00000000 table 26. extended control and status, address 22 (0x16) bit name access description default 15 force 10base-t link high r/w this is a sticky bit. 1 = bypass link integrity test. 0 = enable link integrity test. 0 14 jabber detect disable r/w this is a sticky bit. 1 = disable jabber detect. 0 13 disable 10base-t echo r/w this is a sticky bit. 1 = disable 10base-t echo. 1 12 sqe disable mode r/w 1 = disable sqe transmit. 1 11:10 10base-t squelch control r/w this is a sticky bit. 00 = normal squelch. 01 = low squelch. 10 = high squelch. 11 = reserved. 00 9 reserved 8 eof error ro this bit is self-clearing. 1 = eof error detected. 0 710base-t disconnect state ro this bit is self-clearing. 1 = 10base-t link disconnect detected. 0 610base-t link status ro 1 = 10base-t link active. 0 5:0 reserved ro
vsc8601 datasheet configuration revision 4.1 september 2009 page 50 ? when bits 11:0 are set to 00, the squelc h threshold levels are based on the ieee standard for 10base-t. when set to 01, th e squelch level is decreased, which may improve the bit error rate performance on long loops. when set to 10, the squelch level is increased and may improve the bit error rate in high-noise environments. 4.2.20 extended phy control set 1 the bits in the extended control set cont rol the mac auto-negotiation functioning, sgmii alignment errors, and eeprom status . the following table lists the available settings. note after configuring bit 12 of the extended phy control register set 1, a software reset (register 0, bit 15) must be written to change the device operating mode. bit 1 allows for flexibility in printed circuit boar d layouts because it can reorder the txd pins. 4.2.21 extended phy control set 2 the second set of extended controls is located in register 24 in the main register space for the device. the following table lists the settings and readouts available. table 27. extended phy control 1, address 23 (0x17) bit name access description default 15:9 reserved ro 8 rgmii skew timing compensation enable r/w this is a sticky bit. 0 = disabled. 1 = adds 2 ns delay to the rx_clk and tx_clk pins. cmode 7:6 reserved ro 5actiphy mode enable r/w this is a sticky bit. 1 = enabled. cmode 4:1 reserved ro 0 reserved ro table 28. extended phy control 2, address 24 (0x18) bit name access description default 15:13 100base-tx edge rate control r/w this is a sticky bit. 011 = +5 edge rate (slowest). 010 = +4 edge rate. 001 = +3 edge rate. 000 = +2 edge rate. 111 = +1 edge rate. 110 = default edge rate. 101 = ?1 edge rate. 100 = ?2 edge rate (fastest). 110 12:4 reserved ro
vsc8601 datasheet configuration revision 4.1 september 2009 page 51 4.2.22 interrupt mask the bits in register 25 control the device interrupt mask. the following table lists the settings available. note when bit 25.15 is set, the mdint pin is en abled. when enabled, the state of this pin reflects the state of bit 26.15. clearing this bit only inhibits the mdint pin from being asserted. 3:1 cable length status ro the fo llowing are approximate lengths: 000 = < 10 m. 001 = 10?20 m. 010 = 20?40 m. 011 = 40?80 m. 100 = 80?100 m. 101 = 100?140 m. 110 = 140?180 m. 111 = >180 m. 000 0 1000base-t connector loopback r/w 1 = enabled. 0 table 29. interrupt mask, address 25 (0x19) bit name access description default 15 mdint interrupt status en able r/w this is a sticky bit. 1 = enabled. 0 14 speed state change mask r/w this is a sticky bit. 1 = enabled. 0 13 link state change mask r/w this is a sticky bit. 1 = enabled. 0 12 fdx state change mask r/w this is a sticky bit. 1 = enabled. 0 11 auto-negotiation error mask r/w 1 = enabled. 0 10 auto-negotiation complete mask r/w this is a sticky bit. 1 = enabled. 0 9 inline powered device detect mask r/w this is a sticky bit. 1 = enabled. 0 8:3 reserved ro 2 link speed downshift detect mask r/w this is a sticky bit. 1 = enabled. 0 1 master/slave resolution erro r mask r/w this is a sticky bit. 1 = enabled. 0 0 reserved ro table 28. extended phy control 2, address 24 (0x18) (continued) bit name access description default
vsc8601 datasheet configuration revision 4.1 september 2009 page 52 4.2.23 interrupt status the status of interrupts already written to the device are available for reading from register 26 in the main registers space. th e following table lists the readouts you can expect. the following information applies to the interrupt status bits: ? all set bits in this register are cleared afte r being read (self-clearing). if bit 26.15 is set, the cause of the interrupt ca n be read by reading bits 26.14:0. ? for bits 26.14 and 26.12, bit 0.12 must be set for this interrupt to assert. ? for bit 26.2, bits 4.8:5 must be set for this interrupt to assert. 4.2.24 led control if you are using the simple led method of control, you can control the leds using the following settings. if you are using the enhanced led method, there are different register settings you can use. for information about the enhanced led register settings, see ?enhanced led method select,? page 56. table 30. interrupt status, address 26 (0x1a) bit name access description default 15 interrupt status ro this is a self-clearing bit. 1 = interrupt pending. 0 14 speed state change status ro this is a self-clearing bit. 1 = interrupt pending. 0 13 link state change status ro this is a self-clearing bit. 1 = interrupt pending. 0 12 fdx state change status ro th is is a self-clearing bit. 1 = interrupt pending. 0 11 auto-negotiation error status ro this is a self-clearing bit. 1 = interrupt pending. 10 auto-negotiation complete status ro this is a self-clearing bit. 1 = interrupt pending. 0 9 inline powered device detect status ro this is a self-clearing bit. 1 = interrupt pending. 0 8:3 reserved ro 2 link speed downshift detect stat us ro this is a self-clearing bit. 1 = interrupt pending. 0 1 master/slave resolution error stat us ro this is a self-clearing bit. 1 = interrupt pending. 0 0 reserved ro table 31. led control, address 27 (0x1b) bit name access description default 15:14 reserved ro
vsc8601 datasheet configuration revision 4.1 september 2009 page 53 4.2.25 auxiliary control and status the following table lists the settings available. 13 link 100 led force on (led 2 pin) r/w this is a sticky bit. 1 = forced on. 0 = default. 0 12 link 100 led disable (led2 pin) r/w this is a sticky bit. 1 = disabled. 0 = default. 0 11 link 1000 led force on (led1 pin) r/w this is a sticky bit. 1 = forced on. 0 = default. 0 10 link 1000 led disable (led1 pin) r/w this is a sticky bit. 1 = disabled. 0 = default. 0 9:8 reserved ro 7 activity led force on (led0 pin) r/w this is a sticky bit. 1 = forced on. 0 = default. 0 6 activity led disable (led0 pin) r/w this is a sticky bit. 1 = disabled. 0 = default. 0 5:4 reserved ro 3 led pulse enable rw this is a sticky bit. 0 = normal operation. 1 = leds pulse with a 5khz, 20% duty cycle when active. 0 2 activity led blink enable rw this is a sticky bit. 1 = enable. 0 1 activity led blink rate rw this is a sticky bit. 1 = 10 hz blink rate. 0 = 5 hz blink rate. 0 0reserved ro table 32. auxiliary control and status, address 28 (0x1c) bit name access description default 15 auto-negotiation complete ro duplicate of bit 1.5. 0 14 auto-negotiation disabled ro in verted duplicate of bit 0.12. 0 13 mdi/mdi-x crossover indication ro 1 = mdi/mdi-x crossover performed internally. 0 12 cd pair swap ro 1 = cd pairs are swapped. 0 11 a polarity inversion ro 1 = polarity swap on pair a. 0 10 b polarity inversion ro 1 = polarity swap on pair b. 0 9 c polarity inversion ro 1 = polarity swap on pair c. 0 table 31. led control, address 27 (0x1b) (continued) bit name access description default
vsc8601 datasheet configuration revision 4.1 september 2009 page 54 4.2.26 delay skew status the following table lists the settings available. 4.2.27 reserved address space the bits in register 30 (0x1e) are reserved. 8 d polarity inversion ro 1 = polarity swap on pair d. 0 7:6 reserved ro 5 fdx status ro 1 = full duplex. 0 = half duplex. 0 4:3 speed status ro 00 = speed is 10base-t. 01 = speed is 100base-tx. 10 = speed is 1000base-t. 11 = reserved. 00 2reserved ro 1 sticky reset enable r/w this is a super-sticky bit. 1 = enabled. when enabled, all mii register bits listed as sticky retain their values during a software reset. 0 = disabled. when disabled, all mii register bits listed as sticky change to their default values during a software reset. note that bits listed as super sticky retain their values during a software reset regardless of this setting. 1 0reserved ro table 33. delay skew status, address = 29 (0x1d) bit name access desc ription default 15 reserved ro 14:12 pair a delay skew ro skew in integral symbol times 000 11 reserved ro 10:8 pair b delay skew ro skew in integral symbol times 000 7 reserved ro 6:4 pair c delay skew ro skew in integral symbol times 000 3 reserved ro 2:0 pair d delay skew ro skew in integral symbol times 000 table 32. auxiliary control and status, address 28 (0x1c) (continued) bit name access description default
vsc8601 datasheet configuration revision 4.1 september 2009 page 55 4.3 extended page registers to provide functionality beyond the ieee802. 3-specified 32 registers and main device registers, the vsc8601 device includes an ex tended set of registers that provide an additional 15 register spaces. to access the extended page registers (16e through 30e), enable extended register access by writing 0x0001 to register 31. for more information, see ta b l e 3 5 , page 56. when extended page register access is en abled, reads and writes to registers 16 through 30 affect the extended registers 16e through 30e instead of those same registers in the ieee-specified register spac e. registers 0 through 15 are not affected by the state of the extended page register access. writing 0x0000 to register 31 restores the normal register access. the following table lists the addresses and register names in the extended register page space. these registers are accessible only when the device register 31 is set to 0x0001. table 34. extended registers page space register address register name 16e enhanced led method select 17e enhanced led behavior 18e crc good counter 19e mac resistor calibration control 20e extended phy control 3 21e eeprom interface status and control 22e eeprom data read or write 23e extended phy control 4 24e reserved 25e reserved 26e reserved 27e extended phy control 5 28e rgmii skew control 29e ethernet packet generator (epg) 1 30e ethernet packet generator (epg) 2
vsc8601 datasheet configuration revision 4.1 september 2009 page 56 4.3.1 extended page access the register at address 31 controls the access to the extended page registers for the vsc8601 device. the following table lists the settings available. 4.3.2 enhanced led method select if you are using the enhanced led method of control, you can control the leds using the following settings. if you are using the simple led method, there are different register settings you can use. for information about the simple led register settings, see ?led control,? page 52. the following table shows the led functional modes that can be programmed into any of the device?s led outputs. for more inform ation about accessing or reading the status of the outputs, see table 36, page 56. table 35. extended page access, address 31 (0x1f) bit name access description default 15:0 extended page register access r/w 0x0000 = mii register 16 through 30 accesses main register space 0x0001 = mii register 16 through 30 accesses extended register space 0x0000 table 36. enhanced led method select, address 16e (0x10) bit name access description default 15:12 reserved ro 11:8 led2 mode select r/w this is a sticky bit. select from led modes 0-15 listed below. 0010 7:4 led1 mode select r/w this is a sticky bit. select from led modes 0-15 listed below. 0001 3:0 led0 mode select r/w this is a sticky bit. select from led modes 0-15 listed below. 1010 table 37. available led mode settings mode bit setting led indicates 0 0000 link/activity 1 0001 link1000/activity 2 0010 link100/activity 3 0011 link10/activity 4 0100 link100/1000/activity 5 0101 link10/1000/activity 6 0110 link10/100/activity 7 0111 reserved 8 1000 duplex/collision 9 1001 collision 10 1010 activity
vsc8601 datasheet configuration revision 4.1 september 2009 page 57 4.3.3 enhanced led behavior the following table lists the settings available. 11 reserved 12 1100 autoneg_fault 13 reserved 14 1110 force led off 15 1111 force led on table 38. enhanced led behavior, address 17e (0x11) bit name access description default 15:13 reserved ro 12 led pulsing enable r/w this is a sticky bit. 0 = normal operation. 1 = leds pulse with a 5 khz, 20% duty cycle when active. 0 11:10 led blink / pulse-stretch rate r/w this is a sticky bit. 00 = 2.5 hz blink rate / 400 ms pulse-stretch. 01 = 5 hz blink rate / 200 ms pulse-stretch. 10 = 10 hz blink rate / 100 ms pulse-stretch. 11 = 20 hz blink rate / 50 ms pulse-stretch. 01 9:8 reserved ro 7led2 pulse-stretch / blink select r/w this is a sticky bit. 1 = pulse-stretch. 0 = blink. 1 6led1 pulse-stretch / blink select r/w this is a sticky bit. 1 = pulse-stretch. 0 = blink. 1 5led0 pulse-stretch / blink select r/w this is a sticky bit. 1 = pulse-stretch. 0 = blink. 1 4 led mode r/w this is a sticky bit. 1 = enhanced led method (controlled by mii register 16e and 17e). 0 = simple led method (controlled by mii register 27). 0 3 reserved ro 2led2 combine feature disable r/w this is a sticky bit. 0 = combine enabled (link/activity, duplex/collision). 1 = disable combination (link only, duplex only). 0 table 37. available led mode settings (continued) mode bit setting led indicates
vsc8601 datasheet configuration revision 4.1 september 2009 page 58 note bit 4 must be set to 1 before register 16e and 17e are enabled for enhanced led control. if set to 0, then the led featur es in 16e and 17e are not relevant. if set to 1, then the led features in register 27 are not relevant. 4.3.4 crc good counter register 31e makes it possible to read the contents of the crc good counter; the number of crc routines that have executed successfully. the following table lists the possible readouts. 4.3.5 mac resistor calibration control the following table lists the settings available. 1led1 combine feature disable r/w this is a sticky bit. 0 = combine enabled (link/activity, duplex/collision). 1 = disable combination (link only, duplex only). 0 0led0 combine feature disable r/w this is a sticky bit. 0 = combine enabled (link/activity, duplex/collision). 1 = disable combination (link only, duplex only). 0 table 39. crc good counter, address 18e (0x12) bit name access description default 15 packet since last read ro this is a self-clearing bit. 1 = packet received since last read. 0 14 reserved ro 13:0 crc good counter contents ro this is a self-clearing bit. counter containing the number of packets with valid crcs. this counter does not stop counting and will roll over. 0x000 table 40. mac resistor calibrati on control, address 19e (0x13) bit name access description default 15:14 mac resistor calibration control setting r/w this is a sticky bit. 00 = 50 . 01 = 60 . 10 = 30 . 11 = 45 . cmode 13:0 reserved ro table 38. enhanced led behavior, address 17e (0x11) (continued) bit name access description default
vsc8601 datasheet configuration revision 4.1 september 2009 page 59 4.3.6 extended phy control 3 register 20e controls the actiphy sleep timer, its wake-up timer, the frequency of the clkout signal, and its link speed downshifti ng feature. the following table lists the settings available. 4.3.7 eeprom interface status and control register 21e is used to affect control over device function when you have incorporated a startup eeprom into your design. table 41. extended phy control 3, address 20e (0x14) bit name access description default 15 reserved ro 14:13 actiphy sleep timer r/w this is a sticky bit. 00 = 1 second. 01 = 2 seconds. 10 = 3 seconds. 11 = 4 seconds. 01 12:11 reserved ro 10:9 actiphy link status time-out control r/w 00 = 1 second. 01 = 2 second. 10 = 3 second. 11 = 4 second. 01 8:6 reserved ro 5mac rx_clk disable r/w 1 = rx_clk is held low. 0 = rx_clk is in normal operation. 0 4 enable link speed auto-downshift feature r/w this is a sticky bit. 1 = enable auto link speed downshift from 1000base-t. cmode 3:2 link speed auto-downshift control r/w this is a sticky bit. 00 = downshift after two failed 1000base-t auto-negotiation attempts. 01 = downshift after three failed 1000base-t auto-negotiation attempts. 10 = downshift after four failed 1000base-t auto-negotiation attempts. 11 = downshift after five failed 1000base-t auto-negotiation attempts. 01 1link speed auto-downshift status ro 0 = no downshift. 1 = downshift is required or has occurred. 0 0 reserved ro table 42. eeprom interface status and control, address 21e (0x15) bit name access description default 15 reserved ro
vsc8601 datasheet configuration revision 4.1 september 2009 page 60 4.3.8 eeprom data read/write register 22e in the extended register space enables access to the contents of the external eeprom in your design. the following table lists the writes needed to obtain the data from the external device. 4.3.9 extended phy control 4 the register at address 23e consists of the fourth set bits that control various aspects of inline powering and the crc error counter in the vsc8601 device. 14 re-read eeprom after software reset r/w this is a super-sticky bit. 1 = contents of eep rom to be re-read after software reset. 0 13 enable eeprom access r/w this is a self-clearing bit. 1 = execute read or write eeprom based on the settings of register 21e, bit 12. 0 12 eeprom read or write r/w 1 = read from eeprom. 0 = write to eeprom. 1 11 eeprom ready ro 1 = eeprom is ready for read or write. 1 10:0 eeprom address r/w sets the address of the eeprom to which the read or write is to be directed. 00000000000 table 43. eeprom read or write, address 22e (0x16) bit name access description default 15:8 eeprom read data ro eight-bit data read from eeprom; requires setting register 21e, bit 13. 0x00 7:0 eeprom write data r/w eight-bit da ta to be written to eeprom. 0x00 table 44. extended phy control 4, address 23e (0x17) bit name access description default 15:11 phy address ro phy addres s; latched on reset. cmode 10 inline powered device detection r/w this is a sticky bit. 1 = enabled. 0 9:8 inline powered device detection status ro 00 = searching for devices. 01 = device found; re quires inline power. 10 = device found; does not require inline power. 11 = reserved. 00 table 42. eeprom interface status and control, address 21e (0x15) bit name access description default
vsc8601 datasheet configuration revision 4.1 september 2009 page 61 note bits 9:8 are only valid if bit 10 is set. 4.3.10 reserved extended registers the bits in the extended register page space at addresses 24e, 25e, and 26e (0x18, 0x19, and 0x1a, respectively) are reserved. 4.3.11 extended phy control 5 the following table lists the settings available. 7:0 crc error counter ro this is a self-clearing bit. crc error counter for the ethernet packet generator. the value saturates at 0xff and subsequently clea rs when read and restarts count. 0x00 table 45. extended phy control 5, address 27e (0x1b) bit name access description default 15 hp auto-mdix in forced 10/100 r/w this is a sticky bit. 1 = disabled. for more information about hp auto-mdix, see ?automatic crossover and polarity detection,? page 20. 1 14 reserved ro 13:12 crs behavior control r/w this is a sticky bit. controls the crs behavior. the effect of each setting depends on whether it is half-duplex or full-duplex operation. for half-duplex operation: 00: crs = rx_dv + tx_en 01: crs = rx_dv + tx_en 10: crs = rx_dv 11: crs = rx_dv. for full-duplex operation: 00: crs = rx_dv 01: crs = 0 10: crs = rx_dv 11: crs = 0. 00 11 eeprom present ro 1 = configuration eeprom detected on the eeclk and eedat pins. 0 10 far end loopback mode r/w 1 = enabled. 0 9 picmg 2.16 reduced power mode r/w this is a sticky bit. 1 = enabled. 0 table 44. extended phy control 4, address 23e (0x17) (continued) bit name access description default
vsc8601 datasheet configuration revision 4.1 september 2009 page 62 4.3.12 rgmii skew control the following table lists the settings available. 8:6 100base-tx transmitter amplitude control r/w this is a sticky bit. 011 = reserved. 010 = +4 amplitude setting (l argest). 001 = +3 amplitude setting. 000 = +2 amplitude setting. 111 = +1 amplitude setting. 110 = default amplitude. 101 = ?1 amplitude setting. 100 = ?2 amplitude setting (smallest). 110 5:3 1000base-t transmitter amplitude control r/w this is a sticky bit. 011 = reserved. 010 = +2 amplitude setting (l argest). 001 = +1 amplitude setting. 000 = default amplitude. 111 = ?1 amplitude setting. 110 = ?2 amplitude setting. 101 = ?3 amplitude setting. 100 = ?4 amplitude setting (smallest) 000 2:0 1000base-t edge rate control r/w this is a sticky bit. 011 = +4 edge rate (slowest). 010 = +3 edge rate. 001 = +2 edge rate. 000 = +1 edge rate. 111 = default edge rate. 110 = ?1 edge rate. 101 = ?2 edge rate. 100 = ?3 edge rate (fastest) 111 table 46. rgmii skew control, address 28e (0x1c) bit name access description default 15:14 rgmii tx skew compensation enable r/w this is a sticky bit. 00 = 0 ns. 01 = 1.4 ns. 10 = 1.7 ns. 11 = 2.0 ns. cmode 13:12 rgmii rx skew compensation enable r/w this is a sticky bit. 00 = 0 ns. 01 = 1.4 ns. 10 = 1.7 ns. 11 = 2.0 ns. cmode 11:10 jumbo packet mode r/ w this is a sticky bit. 00 = normal ieee 1.5 kb packet length. 01 = normal ieee 9 kb packet length. 10 = normal ieee 12 kb packet length. 11 = normal ieee 16 kb packet length. 00 9 10base-t no preamble mode r/w this is a sticky bit. 1 = enabled, no preamble required. 0 = disabled, preamble required. 0 table 45. extended phy control 5, address 27e (0x1b) (continued) bit name access description default
vsc8601 datasheet configuration revision 4.1 september 2009 page 63 4.3.13 ethernet packet generator (epg) control 1 the epg control register provides access to and control of various aspects of the epg testing feature. there are two, separate epg control registers. the following table lists the setting available in the first register. the following information applies to the epg control number 1: ? do not run the epg when the vsc8601 device is connected to a live network. ? bit 29e.13 (continuous epg mode control ): when enabled, this mode causes the device to send continuous packets. when disabled, the device continues to send packets only until it reaches the next 10,000-packet increment mark. it then ceases to send packets. ? the six-byte destination address in bits 9:6 is assigned one of 16 addresses in the range of 0xff ff ff ff ff f0 through 0xff ff ff ff ff ff. ? the six-byte source address in bits 5:2 is assigned one of 16 addresses in the range of 0xff ff ff ff ff f0 through 0xff ff ff ff ff ff. ? if any of bits 13:0 are changed while the epg is running (bit 14 is set to 1), bit 14 must be cleared and then set back to 1 for the change to take effect and to restart the epg. 8:0 reserved ro table 47. epg control register 1, address 29e (0x1d) bit name access description default 15 epg enable r/w 1 = enable epg 0 14 epg run or stop r/w 1 = run epg 0 13 transmission duration r/w 1 = continuous (sends in 10,000-packet increments) 0 = send 30,000,000 packets and stop 0 12:11 packet length r/w 00 = 125 bytes 01 = 64 bytes 10 = 1518 bytes 11 = 10,000 bytes (jumbo packet) 0 10 inter-packet gap r/w 1 = 8,192 ns 0 = 96 ns 0 9:6 destination address r/w lowest ni bble of the six-byte destination address 0001 5:2 source address r/w lowest nibbl e of the six-byte destination address 0000 1 payload type r/w 1 = randomly generated payload pattern 0 = fixed based on payload pattern 0 0 bad frame check sequence (fcs) generation r/w 1 = generate packets with bad fcs 0 = generate packets with good fcs 0 table 46. rgmii skew control, address 28e (0x1c) (continued) bit name access description default
vsc8601 datasheet configuration revision 4.1 september 2009 page 64 4.3.14 ethernet packet generator control 2 the register at address 30e consists of the second of bits that provide access to and control over various aspects of the epg testing feature. for information about the first set of epg control bits, see table 47, page 63. the following table lists the settings available. note if any of bits 15:0 in this register are changed while the epg is running (bit 14 of register 29e is set to 1), that bit (29e.14) must first be cleared and then set back to 1 for the change to take effect and to restart the epg. 4.4 cmode the information in this section consists of a detailed description of the methods to configure the vsc8601 device using its cmod e pins. it includes descriptions of the registers that work together with the cm ode pins to control the device function. there are four configuration mode (cmode ) pins on the vsc8601 device. for more information about the physical location of the cmode pins, see ?pin descriptions,? page 84. each cmode pin maps to a configuration bit, which means there are 16 possible settings for the device. 4.4.1 cmode pins an d related functions the following table lists the pin numbers and device functionality that is controlled by each configuration bit. table 48. epg control register 2, address 30e (0x1e) bit name access description default 15:0 epg packet payload r/w data patt ern repeated in the payload of packets generated by the epg 0x00 table 49. cmode configuration pins and device functions cmode pin bit 3 (msb) control bit 2 controls bit 1 controls bit 0 (lsb) controls 3 phy address [3] phy address [4] mac calibration setting[1] mac calibration setting[0] 2 phy address [2] actiphy rgmii clock skew[1] rgmii clock skew[0] 1 phy address [1] link speed downshift speed/duplex modes [1] speed/duplex modes [0] 0 phy address [0] clkout enable advertise asymmetric pause advertise symmetric pause
vsc8601 datasheet configuration revision 4.1 september 2009 page 65 4.4.2 functions and related cmode pins the following table lists the pin and bit setti ngs according to the device function and cmode pin used to configure it. 4.4.3 cmode resistor values to affect the vsc8601 device configuration, find the parameter in table 49, page 64 or in table 50, page 65, and connect the associated pin to the resistor specified in the following table. this sets the bits as shown. table 50. device functions and associated cmode pins function cmode pin bit associated register, bit result phy address [4:0] 3 to 0 3 and 2 sets the phy address. link speed downshift 1 2 register 20e, bit 4 0 = link only according to the auto-negotiation resolution. 1 = enable link speed downshift feature. speed and duplex 1 1 and 0 register 4, bits 8:5 and register 9, bits 9:8 00 = 10/100/1000base-t fdx/hdx. 01 = 10/100/1000base-t fdx; 10/100base-t hdx. 10 = 1000base-t fdx only. 11 = 10/100base-t fdx/hdx. rgmii clock skew 2 1 and 0 register 23, bit 8 00 = no skew on rx_clk and tx_clk. 01 = 1.4 ns skew on rx_clk and tx_clk. 10 = 1.7 ns skew on rx_clk and tx_clk. 11 = 2.0 ns skew on rx_clk and tx_clk. advertise asymmetric pause 01register 4, bit 11 0 = not advertised. 1 = advertised. advertise symmetric pause 00register 4, bit 10 0 = not advertised. 1 = advertised. clkout enable 0 2 register 18, bit 0 0 = disabled. 1 = enabled. actiphy 2 2 register 23, bit 5 0 = disabled. 1 = enabled. mac resistor calibration setting 3 1 and 0 register 19e, bits 15:14 00 = 50 . 01 = 60 . 10 = 30 . 11 = 45 . table 51. cmode resistor valu es and resultant bit settings with cmode pin tied to with 1% resistor value set bit 3 (msb) to: set bit 2 to: set bit 1 to: set bit 0 (lsb) to: vss 0 0 0 0 0 vss 2.26 k 0001 vss 4.02 k 0010 vss 5.90 k 0011
vsc8601 datasheet configuration revision 4.1 september 2009 page 66 using resistors with the cmode pins can be optional in designs that access the device?s mdc/mdio pins. in designs that do this, a ll configurations otherwise affected on the device by using the cmode pins can be changed using the regular device register settings, and all the cmode pins can be pulled to vss (ground). however, the phyaddr [4:0] still requires cmode configuration. 4.5 eeprom the vsc8601 device eeprom interface make s it possible to set up the device to self-configure its internal registers base d on the information programmed into and stored in an external device. to accomplish this, the eeprom is read on power-up or de-assertion of the nreset bit. for field configuration, the eeprom can also be accessed using vsc8601 device registers 21e and 22e. the eeprom used to interface to the vsc8601 device must have a two-wire interface. a device such as the atmel part at24cxxx is suggested. as defined by the interface, data is cl ocked from the vsc8601 device on the falling edge of eeclk. the device determines that an external eeprom is present if eedat is connected to a 4.7 k external pull-up resistor. the eedat pin can be left floating or grounded to indicate that no eeprom is present. 4.5.1 eeprom contents description when an eeprom is present, the vsc8601 device looks for the command header, 0xbdbd at address 0 and 1 of the eeprom. the address is incremented by 256 until the header is found. if the header is not found or no eeprom is connected, the vsc8601 device bypasses the eeprom read step. when an eeprom is present, the vsc8601 device waits for an acknowledgement for approximately three seconds (in accordance wi th the atmel eeprom protocol). if there vss 8.25 k 0100 vss 12.1 k 0101 vss 16.9 k 0110 vss 22.6 k 0111 vdd33 0 1 0 0 0 vdd33 2.26 k 1001 vdd33 4.02 k 1010 vdd33 5.90 k 1011 vdd33 8.25 k 1100 vdd33 12.1 k 1101 vdd33 16.9 k 1110 vdd33 22.6 k 1111 table 51. cmode resistor valu es and resultant bit settings (continued) with cmode pin tied to with 1% resistor value set bit 3 (msb) to: set bit 2 to: set bit 1 to: set bit 0 (lsb) to:
vsc8601 datasheet configuration revision 4.1 september 2009 page 67 is no acknowledgement for three seconds, the vsc8601 device aborts its attempt to connect to the eeprom and reverts to its otherwise normal operating mode. after the header value is found, the two-byte address value shown in the following table indicates the eeprom word address where the base address location for the device is located. at the base address location, the next set of bytes indicates where the configuration data contents to be programmed into the vsc8601 device are located. at the programming location, the first two by tes represent the total number of bytes (11 bits long, with msb first) where the total_number_bytes[10:0] is equal to the number of smi writes multiplied by 3 (one byte for smi port and register address and two bytes for data). data is read from the eeprom sequentially until all smi write commands are completed. 4.5.2 read/write acce ss to the eeprom the vsc8601 device also has the ability to re ad from and write to an eeprom such as an atmel at24cxxx that is directly connec ted to its eeclk and eedat pins. if it is table 52. eeprom configuration contents 10-bit address content (bits 7:0) 00xbd 10xbd 2 phy_addr[4:0], base_address_location[10:8] 3 base_address_location[7:0] (k) address length not specified address length not specified k 00000, config location[10:8] k+1 config_location[7:0] (x) address length not specified address length not specified x 00000, total_number_bytes[10:8] x+1 total_number_bytes [7:0] (m) x+2 register address a x+3 data[15:8] to be writte n to register address a x+4 data[7:0] to be writte n to register address a x+5 register address b x+6 data[15:8] to be writte n to register address b x+7 data[7:0] to be writte n to register address b address length not specified x+(m?2) register address x x+(m?1) data[15:8] to be writ ten to register address x x+m data[7:0] to be writte n to register address x address length not specified address length not specified max address
vsc8601 datasheet configuration revision 4.1 september 2009 page 68 required to be able to write to the eeprom, refer to the eeprom?s specific datasheet to ensure that write protection on the eeprom is not set. the following illustration shows the interact ion of the vsc8601 device and the eeprom. figure 17. eeprom read and write register flow to read a value from a specific address of the eeprom: 1. read the vsc8601 device register bit 21e.11 and ensure that it is set. 2. write the eeprom address to be read to register bits 21e.10:0. 3. set both register bits 21e.12 and 21e.13 both to 1. 4. when register bit 21e.11 changes to 1, read the 8-bit data value found at register bits 22e.15:8. this is the contents of the address just read by the phy. to write a value to a specific address of the eeprom: 1. read the vsc8601 device register bit 21e.11 and ensure that it is set. 2. write the address to be written to register bits 21e.10:0. 3. set register bit 21e.12 to 0. 4. set register bits 22e.7:0 with the 8- bit value to be written to the eeprom. 5. set register bit 21e.13 to 1. 6. to avoid collisions during read and write transactions, always wait until register bit 21e.11 changes to 1 before performing another eeprom read or write operation. wait for ready 21e.11 = 0 21e.11 = 1 read or write 21e.10:0 = write address 21e.12 = 0 22e.7:0 = data to write write eeprom data 21e.10:0 = address to read 21e.12 = 1 21e.13 = 1 21e.13 = 1 wait for ready 21e.11 = 0 21e.11 = 1 read eeprom data read data = 22e.15:8 start
vsc8601 datasheet electrical specifications revision 4.1 september 2009 page 69 5 electrical specifications this section provides the dc characteristics, ac characteristics, recommended operating conditions, and stress ratings for th e vsc8601 device. it includes information on the various timing functions of the device. 5.1 dc characteristics in addition to any parameter-specific co nditions, the specifications listed in the following table may be considered valid only in the environment characterized by the specifications listed as recommended operat ing conditions for the vsc8601 device. for more information about the recommended operating conditions, see ?operating conditions,? page 82. 5.1.1 vddio at 3.3 v in addition to any parameter-specific co nditions, the specifications listed in the following table may be considered valid only when all of these apply: ?v ddio is 3.3 v ?v dd33 is 3.3 v ?v dd12 is 1.2 v ?v dd12a is 1.2 v ?v ddreg is 3.3 v table 53. dc characteristics for vdd33, vddiomac, or vddiomicro at 3.3 v parameter symbol minimum maximum unit condition output high voltage v oh 2.4 3.6 v i oh = ?4 ma output low voltage v ol 00.5vi ol = 4 ma input high voltage v ih 2.0 5.0 v for jtag pins input high voltage v ih 2.1 3.6 v for all other input pins input low voltage v il ?0.3 0.9 v input leakage current i ileak ?43 43 a internal resistor included output leakage current i oleak ?43 43 a internal resistor included output low current drive strength i ol 11 ma output high current drive strength i oh ?20 ma
vsc8601 datasheet electrical specifications revision 4.1 september 2009 page 70 5.1.2 vddio at 2.5 v in addition to any parameter-specific co nditions, the specifications listed in the following table may be considered valid only when all of these apply: ?v ddio is 2.5 v ?v dd33 is 3.3 v ?v dd12 is 1.2 v ?v dd12a is 1.2 v ?v ddreg is 3.3 v 5.2 current consumption the current consumption values listed in th is section are based on nominal values and the phy operating with full-duplex enabled and a 64-bit random data pattern at 100% utilization. values are grouped by the type of link and whether the on-chip switching regulator is enabled. 5.2.1 consumption with 1000base-t link the following table shows the current consumption values with a 1000base-t link and the on-chip switching regulator enabled. table 54. dc characteristics for v ddiomac or vddiomicro at 2.5 v parameter symbol minimum maximum unit condition output high voltage v oh 2.0 2.8 v i oh = ?1.0 ma output low voltage v ol ?0.3 0.4 v i ol = 1.0 ma input high voltage v ih 2.0 3.0 v for all other pins input low voltage v il ?0.3 0.7 v input leakage current i ileak ?35 35 a internal resistor included output leakage current i oleak ?35 35 a internal resistor included output low current drive strength i ol 9ma output high current drive strength i oh ?11 ma table 55. current consumption: 1000base-t, regulator enabled parameter symbol typical unit current with v dd33 at 3.3 v i vdd33 115 ma current with v ddreg i vddreg 75 ma current with v ddiomac at 3.3 v i vddiomac 32 ma current with v ddiomac at 2.5 v i vddiomac 23 ma current with v ddiomicro at 3.3 v i vddiomicro < 1 ma
vsc8601 datasheet electrical specifications revision 4.1 september 2009 page 71 the following table shows the current consumption values with a 1000base-t link and the on-chip switching regulator disabled. 5.2.2 consumption with 100base-tx link the following table shows the current cons umption values with a 100base-tx link and the on-chip switching regulator enabled. the following table shows the current cons umption values with a 100base-tx link and the on-chip switching regulator disabled. current with v ddiomicro at 2.5 v i vddiomicro < 1 ma total power at 3.3 v 734 mw total power at 2.5 v 686 mw table 56. current consumption: 1000base-t, regulator disabled parameter symbol typical unit current with v dd33 at 3.3 v i vdd33 115 ma current with v ddreg i vddreg < 1 ma current with v dd12 at 1.2 v i vdd12 136 ma current with v dd12a at 1.2 v i vdd12a 34 ma current with v ddiomac at 3.3 v i vddiomac 32 ma current with v ddiomac at 2.5 v i vddiomac 23 ma current with v ddiomicro at 3.3 v i vddiomicro < 1 ma current with v ddiomicro at 2.5 v i vddiomicro < 1 ma total power at 3.3 v 689 mw total power at 2.5 v 641 mw table 57. current consumption: 100base-tx, regulator enabled parameter symbol typical unit current with v dd33 at 3.3 v i vdd33 94 ma current with v ddreg i vddreg 35 ma current with v ddiomac at 3.3 v i vddiomac 5ma current with v ddiomac at 2.5 v i vddiomac 3ma current with v ddiomicro at 3.3 v i vddiomicro < 1 ma current with v ddiomicro at 2.5 v i vddiomicro < 1 ma total power at 3.3 v 442 mw total power at 2.5 v 433 mw table 58. current consumption: 100base-tx, regulator disabled parameter symbol typical unit current with v dd33 at 3.3 v i vdd33 94 ma table 55. current consumption: 1000base-t, regulator enabled (continued) parameter symbol typical unit
vsc8601 datasheet electrical specifications revision 4.1 september 2009 page 72 5.2.3 consumption with 10base-t link the following table shows the current consum ption values with a 10base-t link and the on-chip switching regulator enabled. the following table shows the current consum ption values with a 10base-t link and the on-chip switching regulator disabled. current with v ddreg i vddreg < 1 ma current with v dd12 at 1.2 v i vdd12 55 ma current with v dd12a at 1.2 v i vdd12a 24 ma current with v ddiomac at 3.3 v i vddiomac 5ma current with v ddiomac at 2.5 v i vddiomac 3ma current with v ddiomicro at 3.3 v i vddiomicro < 1 ma current with v ddiomicro at 2.5 v i vddiomicro < 1 ma total power at 3.3 v 422 mw total power at 2.5 v 413 mw table 59. current consumption: 10base-t, regulator enabled parameter symbol typical unit current with v dd33 at 3.3 v i vdd33 155 ma current with v ddreg i vddreg 19 ma current with v ddiomac at 3.3 v i vddiomac < 1 ma current with v ddiomac at 2.5 v i vddiomac < 1 ma current with v ddiomicro at 3.3 v i vddiomicro < 1 ma current with v ddiomicro at 2.5 v i vddiomicro < 1 ma total power at 3.3 v 573 mw total power at 2.5 v 573 mw table 60. current consumption: 10base-t, regulator disabled parameter symbol typical unit current with v dd33 at 3.3 v i vdd33 155 ma current with v ddreg i vddreg < 1 ma current with v dd12 at 1.2 v i vdd12 24 ma current with v dd12a at 1.2 v i vdd12a 18 ma current with v ddiomac at 3.3 v i vddiomac < 1 ma current with v ddiomac at 2.5 v i vddiomac < 1 ma current with v ddiomicro at 3.3 v i vddiomicro < 1 ma current with v ddiomicro at 2.5 v i vddiomicro < 1 ma total power at 3.3 v 562 mw total power at 2.5 v 562 mw table 58. current consumption: 100base-tx, regulator disabled (continued) parameter symbol typical unit
vsc8601 datasheet electrical specifications revision 4.1 september 2009 page 73 5.2.4 consumption with no link and actiphy enabled the following table shows the current consumption values with no link, actiphy enabled, and the on-chip switching regulator enabled. the following table shows the current consumption values with no link, actiphy enabled, and the on-chip switching regulator disabled. 5.2.5 consumption with no link and actiphy disabled the following table shows the current consumption values with no link, actiphy disabled, and the on-chip switching regulator enabled. table 61. current consumption: no link , actiphy enabled, regulator enabled parameter symbol typical unit current with v dd33 at 3.3 v i vdd33 21 ma current with v ddreg i vddreg 21 ma current with v ddiomac at 3.3 v i vddiomac 12 ma current with v ddiomac at 2.5 v i vddiomac 8ma current with v ddiomicro at 3.3 v i vddiomicro < 1 ma current with v ddiomicro at 2.5 v i vddiomicro < 1 ma total power at 3.3 v 178 mw total power at 2.5 v 158 mw table 62. current consumption: no link , actiphy enabled, regulator disabled parameter symbol typical unit current with v dd33 at 3.3 v i vdd33 21 ma current with v ddreg i vddreg < 1 ma current with v dd12 at 1.2 v i vdd12 27 ma current with v dd12a at 1.2 v i vdd12a 20 ma current with v ddiomac at 3.3 v i vddiomac 12 ma current with v ddiomac at 2.5 v i vddiomac 8ma current with v ddiomicro at 3.3 v i vddiomicro < 1 ma current with v ddiomicro at 2.5 v i vddiomicro < 1 ma total power at 3.3 v 165 mw total power at 2.5 v 146 mw table 63. current consumption: no link , actiphy disabled, regulator enabled parameter symbol typical unit current with v dd33 at 3.3 v i vdd33 107 ma current with v ddreg i vddreg 22 ma current with v ddiomac at 3.3 v i vddiomac 12 ma current with v ddiomac at 2.5 v i vddiomac 8ma current with v ddiomicro at 3.3 v i vddiomicro < 1 ma
vsc8601 datasheet electrical specifications revision 4.1 september 2009 page 74 the following table shows the current consumption values with no link, actiphy disabled, and the on-chip switching regulator disabled. 5.2.6 consumption in power-down mode the following table shows the current consumption values in power-down mode (register address 0.11 = 1) with the regulator enabled. current with v ddiomicro at 2.5 v i vddiomicro < 1 ma total power at 3.3 v 466 mw total power at 2.5 v 446 mw table 64. current consumption: no link , actiphy disabled, regulator disabled parameter symbol typical unit current with v dd33 at 3.3 v i vdd33 107 ma current with v ddreg i vddreg < 1 ma current with v dd12 at 1.2 v i vdd12 27 ma current with v dd12a at 1.2 v i vdd12a 23 ma current with v ddiomac at 3.3 v i vddiomac 12 ma current with v ddiomac at 2.5 v i vddiomac 8ma current with v ddiomicro at 3.3 v i vddiomicro < 1 ma current with v ddiomicro at 2.5 v i vddiomicro < 1 ma total power at 3.3 v 453 mw total power at 2.5 v 433 mw table 65. current consumption: power-down, regulator enabled parameter symbol typical unit current with v dd33 at 3.3 v i vdd33 15 ma current with v ddreg i vddreg 15 ma current with v dd12 at 1.2 v i vdd12 0ma current with v dd12a at 1.2 v i vdd12a 0ma current with v ddiomac at 3.3 v i vddiomac 0ma current with v ddiomac at 2.5 v i vddiomac 0ma current with v ddiomicro at 3.3 v i vddiomicro 0ma current with v ddiomicro at 2.5 v i vddiomicro 0ma total power at 3.3 v 99 mw table 63. current consumption: no link , actiphy disabled, regulator enabled parameter symbol typical unit
vsc8601 datasheet electrical specifications revision 4.1 september 2009 page 75 the following table shows the current consumption values in power-down mode (register address 0.11 = 1) with the regulator disabled. 5.2.7 consumption in reset state the following table shows the current consumption values in the reset state (nreset pin pulled low). 5.3 ac characteristics the ac specifications are grouped according to specific device pins and associated timing characteristics. table 66. current consumption: power-down, regulator disabled parameter symbol typical unit current with v dd33 at 3.3 v i vdd33 15 ma current with v ddreg i vddreg 0ma current with v dd12 at 1.2 v i vdd12 12 ma current with v dd12a at 1.2 v i vdd12a 20 ma current with v ddiomac at 3.3 v i vddiomac 0ma current with v ddiomac at 2.5 v i vddiomac 0ma current with v ddiomicro at 3.3 v i vddiomicro 0ma current with v ddiomicro at 2.5 v i vddiomicro 0ma total power at 3.3 v 87.9 mw table 67. current consumption: reset state parameter symbol typical unit current with v dd33 at 3.3 v i vdd33 7ma current with v ddreg i vddreg 0ma current with v dd12 at 1.2 v i vdd12 0ma current with v dd12a at 1.2 v i vdd12a 0ma current with v ddiomac at 3.3 v i vddiomac 0ma current with v ddiomac at 2.5 v i vddiomac 0ma current with v ddiomicro at 3.3 v i vddiomicro 0ma current with v ddiomicro at 2.5 v i vddiomicro 0ma total power at 3.3 v 23.1 mw
vsc8601 datasheet electrical specifications revision 4.1 september 2009 page 76 5.3.1 reference clock input the following table lists the specifications for the reference clock input frequency including various frequencies, duty cycle, and accuracy. when using the 25 mhz crystal clock input opti on, the additional specifications in the following table are required. 5.3.2 clock output the specifications in the following table show the ac characteristics for the clock output of the vsc8601 device. table 68. ac characteristics for refclk input parameter symbol minimum typical maximum unit frequency with 25 mhz input f clk25 25 mhz frequency with 125 mhz input f clk125 125 mhz frequency accuracy f tol 50 ppm duty cycle % duty 40 60 % rise time with 25 mhz input (20% to 80%) t r25 4ns rise time with 125 mhz input (20% to 80%) t r125 1ns table 69. ac characteristics for refc lk input with 25 mhz clock input parameter minimum typical maximum unit crystal parallel load capacitance 18 20 pf crystal equivalent se ries resistance 10 30 table 70. ac characteristics for the clkout pin parameter symbol minimum typical maximum unit condition clkout frequency f clk 125.00 mhz 125 mhz output clock clkout cycle time t cyc 8.0 ns 125 mhz output clock frequency stability f stability 50 ppm duty cycle % duty 44 50 56 % clock rise and fall times (20% to 80%) t r and t f 1ns to t a l j i t t e r j clk 217 600 ps measured peak-to-peak, time interval error
vsc8601 datasheet electrical specifications revision 4.1 september 2009 page 77 5.3.3 jtag interface the following table lists the characteristics for the jtag testing feature. for information about the jtag interface timing, see figure 18, page 77. figure 18. jtag interface timing 5.3.4 smi interface use the information in the following table when incorporating the vsc8601 device smi interface into your own design. for inform ation about the smi interface timing, see figure 19, page 78. table 71. ac characteristic s for the jtag interface parameter symbol minimum maximum unit tck frequency f clk 10 mhz tck cycle time t cyc 100 ns tck time high t wh 45 ns tck time low t wl 45 ns setup time to tck rising t su 10 ns hold time from tck rising t h 10 ns tck to tdo valid t co 15 ns table 72. ac characteristic s for the smi interface parameter symbol minimum typical maximum unit condition mdc frequency (1) f clk 2.5 12.5 mhz mdc cycle time t cyc 80 400 ns tck tdi tms t su t h t cyc t wh t wl t co tdo
vsc8601 datasheet electrical specifications revision 4.1 september 2009 page 78 figure 19. smi interface timing 5.3.5 device reset the following specifications apply to the device reset functionality. for more information about the reset timing, see figure 20, page 79. mdc time high t wh 20 50 ns mdc time low t wl 20 50 ns setup to mdc rising t su 10 ns hold from mdc rising t h 10 ns mdc rise time t r 100 t cyc 10% (1) ns for mdc = 0 ? 1 mhz for mdc = 1 mhz ? f clk (max) mdc fall time t f 100 t cyc 10% (1) mdc to mdio valid t co 10 300 ns time dependant on value of external pull-up resistor on mdio pin 1. for f clk above 1 mhz, the maximum rise time and fall time is in relation to the fre quency of the mdc clock period. for example, if f clk is 2 mhz, the maximum clock rise time and fall time is 50 ns. table 73. ac characteristics for device reset parameter symbol minimum maximum unit condition nreset assertion time t reset 100 ns wait time between nreset de-assert and access of the smi interface t wait 20 220 ms ms register 21e.14 = 0 register 21e.14 = 1 table 72. ac characteristic s for the smi interface (continued) parameter symbol minimum typical maximum unit condition t su data mdc t h t wl t wh t co data t cyc mdio (write) mdio (read)
vsc8601 datasheet electrical specifications revision 4.1 september 2009 page 79 figure 20. reset timing note the nreset and nsreset are mutually exclusive. soft reset (pin) assertion t sreset_assert 4ms soft reset (pin) de-assertion t sreset_deassert 4ms reset rise time t rst_rise 0 25 ms ms if reg_en pin = 0 if reg_en pin = 1 measured from a 10% level to a 90% level supply stable time t vddstable 10 ms wait time between soft reset pin de-assert and access of the smi interface t swait 4 300 200 200 s s ms ms registers 28.1 = 1, 21e.14 = 0 registers 28.1 = 0, 21e.14 = 0 registers 28.1 = 0, 21e.14 = 1 registers 28.1 = 1, 21e.14 = 1 soft reset mii register 0.15 assertion t sreg_reset 100 ns wait time between soft reset (mii register 0.15) de-assert and access to the smi interface t sreg_wait 4 300 200 200 s s ms ms registers 18.1 = 1, 21e.14 = 0 registers 18.1 = 0, 21e.14 = 0 registers 18.1 = 0, 21e.14 = 1 registers 18.1 = 1, 21e.14 = 1 table 73. ac characteristics for device reset (continued) parameter symbol minimum maximum unit condition nreset t reset refclk t wait mdio soft reset (mii register 0.15) t sreg_reset t sreg_wait undefined state mdc nsreset t sreset_assert t swait t sreset_deassert t rst_rise vdd33 t vddstable
vsc8601 datasheet electrical specifications revision 4.1 september 2009 page 80 5.3.6 rgmii uncompensated the following table lists the characteristics when using the device in rgmii uncompensated mode. for more informatio n about the rgmii uncompensated timing, see figure 21, page 81. table 74. ac characteristic s for rgmii uncompensated parameter symbol minimum typical maximum unit condition clock frequency 125 25 2.5 mhz 1000base-t operation 100base-tx operation 10base-t operation 1000base-t duty cycle t duty1000 45 50 55 % at room temperature and nominal supply and register 28e.13:12 set to 10 or 11 1000base-t duty cycle t duty1000 40 50 60 % register 28e.13:12 set to 00 or 01 10/100base-t duty cycle t duty10/100 40 50 60 % data to clock output skew (at phy) t skew t ?500 0 500 ps data to clock output skew (at receiver) t skew r1.0 1.8 2.6ns tx_clk switching threshold v thresh 1.25 1.65 v v v ddiomac = 2.5 v v ddiomac = 3.3 v tx_clk rise and fall times t r and t f 750 ps
vsc8601 datasheet electrical specifications revision 4.1 september 2009 page 81 figure 21. rgmii uncompensated timing 5.3.7 rgmii compensated the following table lists the characteristics when using the device in rgmii compensated mode. for more information about the rgmii compensated timing, see figure 22, page 82. table 75. ac characteristic s for rgmii compensated parameter symbol minimum typical maximum unit condition data to clock output setup (at phy integrated delay) t setup t1.2 2.0 3 ns data to clock output setup (at receiver integrated delay) t setup r1.0 2.0 3 ns data to clock output hold (at transmitter integrated delay) t hold t1.2 2.0 3 ns t skew t txd[3:0] tx_ctl tx_clk (at transmitter) tx_clk (at receiver) t skew r txd[3:0] txd[7:4] txen txerr t skew t rxd[3:0] rx_ctl rx_clk (at transmitter) rx_clk (at receiver) t skew r rxd[3:0] rxd[7:4] rxdv rxerr t cyc 80% 20% t r , t f v thresh
vsc8601 datasheet electrical specifications revision 4.1 september 2009 page 82 figure 22. rgmii compensated timing 5.4 operating conditions the following table lists the recommended operating conditions for the vsc8601 device. data to clock output hold (at phy integrated delay) t hold r1.0 2.0 3 ns tx_clk switching threshold v thresh 1.25 1.65 v v v ddiomac = 2.5 v v ddiomac = 3.3 v table 76. recommended operating conditions parameter symbol minimum typical maximum unit power supply voltage for v ddiomicro at 2.5 v v ddiomicro 2.37 2.5 2.63 v table 75. ac characteristic s for rgmii compensated (continued) parameter symbol minimum typical maximum unit condition t setup t txd[3:0] tx_ctl tx_clk (at transmitter) tx_clk (at receiver) t setup r txd[3:0] txd[7:4] txen txerr rxd[3:0] rx_ctl rx_clk (at transmitter) rx_clk (at receiver) rxd[3:0] rxd[7:4] rxen rxerr tx_clk with internal delay added t hold r t hold t t setup t rx_clk with internal delay added t hold r t hold t delay = 2.0 ns delay = 2.0 ns v thresh
vsc8601 datasheet electrical specifications revision 4.1 september 2009 page 83 5.5 stress ratings this section contains the stress ratings for the vsc8601 device. warning stresses listed in the following table may be applied to devices one at a time without causing permanent damage. functiona lity at or exceeding the values listed is not implied. exposure to these values for ex tended periods may affect device reliability. warning this device can be damaged by electrostatic discharge (esd) voltage. vitesse recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures may adversely affect reliability of the device. power supply voltage for v ddiomicro at 3.3 v v ddiomicro 3.0 3.3 3.6 v power supply voltage for v ddiomac at 2.5 v v ddiomac 2.37 2.5 2.63 v power supply voltage for v ddiomac at 3.3 v v ddiomac 3.0 3.3 3.6 v power supply voltage for v dd33 v dd33 3.0 3.3 3.6 v power supply voltage for v ddreg v ddreg 3.0 3.3 3.6 v power supply voltage for v dd12 v dd12 1.14 1.2 1.26 v power supply voltage for v dd12a v dd12a 1.14 1.2 1.26 v operating temperature (1) t0 90c 1. lower limit of specification is ambient temp erature, and upper limi t is case temperature. table 77. stress ratings parameter symbol minimum maximum unit dc input voltage on v ddiomicro supply pin v ddiomicro ?0.5 4.0 v dc input voltage on v ddiomac supply pin v ddiomac ?0.5 4.0 v dc input voltage on v dd33 supply pin v dd33 ?0.5 4.0 v dc input voltage on v ddreg supply pin v ddreg ?0.5 4.0 v dc input voltage on v dd12 supply pin v dd12 ?0.5 1.5 v dc input voltage on v dd12a supply pin v dd12a ?0.5 1.5 v dc input voltage on jtag pins, 5 v tolerant v dd (5 v) ?0.5 5.5 v dc input voltage on any non-supply pin v dd (pin) ?0.5 v dd + 0.5 v storage temperature t s ?65 150 o c electrostatic discharge vo ltage, charged device model v esd_cdm ?500 500 v electrostatic discharge voltage, human body model v esd_hbm ?1500 1500 v table 76. recommended operating conditions (continued) parameter symbol minimum typical maximum unit
vsc8601 datasheet pin descriptions revision 4.1 september 2009 page 84 6 pin descriptions the vsc8601 device has 64 pins, which are described in this section. the pin information is also provided as an attached microsoft excel file, so that you can copy it electronically. in adobe read er, double-click the attachment icon. 6.1 pin diagram the following illustration shows the pin diagram for the vsc8601 device. note the exposed pad is internally connected to ground and should be connected to vss on the board as well. figure 23. pin diagram vdd33 tdo tdi vdd12 tms tck ntrst nreset eedat eeclk vddiomicro mdint mdc mdio vdd12 vddiomac nc pllmode reg_out vddreg reg_en oscen/clkou t led0 led1 led2 vdd33 cmode3 cmode2 cmode1 cmode0 vdd12 vddiomac nsreset tx_ctl txd0 txd1 txd2 txd3 tx_clk vddiomac rx_clk rxd0 rxd1 rxd2 rxd3 vddiomac rx_ctl vss ref_filt ref_rext vdd33 vdd12a txvpa txvna txvpb txvnb vdd33 txvpc txvnc txvpd txvnd vdd33 xtal2 xtal1/refclk 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 vsc8601 exposed pad
vsc8601 datasheet pin descriptions revision 4.1 september 2009 page 85 6.2 pins by function this section contains the functional pi n descriptions for the vsc8601 device. the following table contains notations for definitions of the various pin types. 6.2.1 twisted pair interface the following table lists the device pins associated with the device two-wire, twisted pair interface. table 78. pin type symbols symbol pin type description i input input with no on-chip pu ll-up or pull-down resistor. i/o input and output input and output signal with no on -chip pull-up or pull-down resistor. i pu input with pull-up input with on-chip 100 k pull-up resistor to vddio. i pd input with pull-down input with on-chip 100 k pull-down resistor to vss. i pd /o bidirectional with pull-down input and output signal with on-chip 100 k pull-down resistor to vss. i pu /o bidirectional with pull-up input and output signal with on-chip 100 k pull-up resistor to vddio or vdd33. o output output signal. o zc impedance controlled output integrated (on-chip) source series termin ated, output signal. od open drain open drain output. os open source open source output. a diff analog differential analog differential si gnal pair for twisted pair interface. a bias analog bias analog bias pin. i a analog input analog input for se nsing variable voltage levels. i pu5v input with pull-up input with on-chip 100 k pull-up resistor to vdd33. these pins are 5 v tolerant. o cryst crystal output crystal clock output pi n. if not used, leave unconnected. nc no connect no connect pins must be left floating. table 79. twisted pair interface pins pin name type description 53 txvpa a diff tx/rx channel a positive signal 54 txvna a diff tx/rx channel a negative signal 55 txvpb a diff tx/rx channel b positive signal 56 txvnb a diff tx/rx channel b negative signal 58 txvpc a diff tx/rx channel c positive signal 59 txvnc a diff tx/rx channel c negative signal 60 txvpd a diff tx/rx channel d positive signal 61 txvnd a diff tx/rx channel d negative signal
vsc8601 datasheet pin descriptions revision 4.1 september 2009 page 86 6.2.2 rgmii mac interface the following table lists the device pins asso ciated with the rgmii mac interface. note that the pins in this table are referenced to vddio mac and can be set to a 2.5 v or 3.3 v power supply. table 80. rgmii mac interface pins pin name type description 20 21 22 23 rxd3 rxd2 rxd1 rxd0 o zc multiplexed receive data. bits[3:0] are synchronously output on the rising edge of rx_clk and bits[7:4] on the falling edge of rx_clk. 24 rx_clk o zc receive clock. receive data is sourced from the phy synchronously on the rising edge of rx_clk and is the recovered clock from the media. 18 rx_ctl o zc multiplexed receive data va lid, receive error. this output is sampled by the mac on opposite edges of rx_clk to indicate two receive conditions from the phy: 1. on the rising edge of rx_clk, this output serves as rxdv and signal s valid data is available on the rxd input data bus. 2. on the fallin g edge of rx_clk, this output signals a receive error from the phy, based on a logical derivative of rxdv and rxer, as stated by the rgmii specification. 27 28 29 30 txd3 txd2 txd1 txd0 i pd multiplexed transmit data. bits[3:0] are synchronously output on the rising edge of tx_clk and bits[7:4] on the falling edge of tx_clk. 26 tx_clk i transmit clock. this clock is 2.5 mhz for 10 mbps mode, 25 mhz for 100 mbps mode, and 125 mhz for 1000 mbps mode. if le ft unconnected, these pins require a pull-down resistor to ground. 31 tx_ctl i pd multiplexed transmit enable, transmit error. this input is sampled by the phy on opposite edges of tx_clk to indicate two transmit conditions of the mac: 1. on the rising edge of tx_clk, this input serves as txen, indicating valid data is available on the txd input data bus. 2. on the falling edge of tx_clk, this input signals a transmit error from the mac, based on a logical derivative of txen and txer, as stated by the rgmii specification. 32 nsreset i pu soft reset. active low input that places the device in a low-power state. al though the device is powered down, the stic ky serial management interface registers retain their value.
vsc8601 datasheet pin descriptions revision 4.1 september 2009 page 87 6.2.3 serial management interface (smi) the following table lists the device pins associated with the device serial management interface (smi). note that the pins in this table are referenced to vddio micro and can be set to a 2.5 v, or 3.3 v power supply. 43 oscen/clkout i pu /o oscen. this pin is sample d on the rising edge of nreset. if high (or left floating), then the on-chip oscillator circuit is enabled. if low, the oscillator circuit is disabl ed and the device must be supplied with a 25 mhz or 125 mhz reference clock to the refclk pin. clkout. after nreset is deasserted and oscen state is established, th is pin becomes the clock output. the clock output can be enabled or disabled through a cmode pi n setting. also, it can generate a reference cloc k frequency of 125 mhz. this pin is not active when nreset is asserted. when disabled, the pin is held low. table 81. smi pins pin name type description 13 mdc i pu management data clock. a 0 mhz to 12.5 mhz reference input is used to clock serial mdio data into and out of the phy. 14 mdio i/o management data input/ output pin. serial data is written or read from this pin bidirectionally between the phy and station manager, synchronously on the positive edge of mdc. one external pull-up re sistor is required at the station manager, and its value de pends on the mdc clock frequency and the total sum of the capacitive loads from the mdio pins. 12 mdint os/od management interru pt signal. afte r reset, the device configures this pi n, along with others from other devices, as active -low (open drain) or active-high (open source) ba sed on the polarity of an external 10 k resistor connection. these pins can be tied together in a wired-or configuration with only a single pull-up or pull-down resistor. 9 eedat i pd /o (optional) eeprom serial i/o data. used to configure phys in a system without a station manager. connect to the sda pin of the atmel ?at24cxxx? serial eeprom device family. the vsc8601 determines that an external eeprom is present by monitoring the eedat pin at power-up or when nreset is de-asserted. if eedat has a 4.7 k external pull-up resistor, the vsc8601 assumes an eeprom is present. the eedat pin can be left floating or grounded to indicate no eeprom. table 80. rgmii mac interface pins (continued) pin name type description
vsc8601 datasheet pin descriptions revision 4.1 september 2009 page 88 6.2.4 jtag the following table lists the device pins associated with the device jtag testing facility. 6.2.5 miscellaneous the following table lists the device pins associated with a particular interface or facility on the device. 10 eeclk o zc (optional) eeprom serial output clock. used to configure phys in a system without a station manager. connect to the scl pin of the atmel ?at24cxxx? serial eeprom device family. 8 nreset i pu device reset. active low input that powers down the device and sets the register bits to their default state. table 82. jtag pins pin name type description 3 tdi i pu5v jtag test serial data input. 2 tdo o jtag test serial data output. 5 tms i pu5v jtag test mode select. 6 tck i pu5v jtag test clock input. 7 ntrst i pu5v jtag reset. if jt ag is not used, then tie this pin to vss (ground) with a pull-down resistor. table 83. miscellaneous pins pin name type description 38 37 36 35 cmode3 cmode2 cmode1 cmode0 i a configuration mode (cmode) pins. for more information, see ?cmode,? page 64. 64 xtal1/refclk i crystal oscillator input. if oscen=high, then a 25 mhz parallel resonant crystal with 50 ppm frequency tolerance shou ld be connected across xtal1 and xtal2. a 33 pf capacitor should also tie the xtal1 pin to ground. reference clock input. if oscen=low, the clock input frequency can either be 25 mhz (pllmode=0) or 125 mhz (pllmode is high). 63 xtal2 o cryst crystal oscillator output . the crystal should be connected across xtal 1 and xtal2. a 33 pf capacitor should also tie the xtal2 pin to ground. if not using a crystal oscillator, this output pin can be left floating if driving xt al1/refclk with a reference clock. table 81. smi pins (continued) pin name type description
vsc8601 datasheet pin descriptions revision 4.1 september 2009 page 89 6.2.6 power supply the following table lists the device power supply pins. 47 pllmode i pll mode input sele ct. sampled on power-up or reset. if pllmode is low, then refclk must be 25 mhz. if pllmode is high , then refclk must be 125 mhz. if a crystal or an external 25 mhz clock is used, pllmode must be pulled low. if an external 125 mhz clock is used, pllmode must be pulled high. 40 41 42 led2 led1 led0 o led direct-drive outputs. al l leds pins are active-low. for more information ab out led operation, see ?led interface,? page 28. 50 ref_rext a bias reference external connec ts to an external 2 k (1%) resistor to analog ground. 49 ref_filt a bias reference filter connects to an external 1 f capacitor to analog ground. 44 reg_en i regulator enable. active high input enables the on-chip switching regulato r and generates a 1.2 v supply voltage. 46 reg_out a bias regulator output. when reg_en is enabled, reg_out supplies a 1.2 v supply that has been regulated from the 3.3 v su pply. when connecting to the 1.2 v supply pins, additi onal requirements are a 4.7 h to 5.1 h inductor in series as well as 10 f and 1 f capacitors to ground. the on-chip switching regulator is optional, and 1.2 v power can be supplied externally. 48 nc nc no connects. do not connect them together or to ground. leave these pins unconnected (floating). table 84. power supply pins pin name type description 1, 39, 51, 57, 62 vdd33 3.3 v general 3.3 v supply. 45 vddreg 3.3 v on-chip switch ing regulator 3.3 v supply. 11 vddiomicro 3.3 v 2.5 v i/o micro power supply. 16, 19, 25, 33 vddiomac 3.3 v 2.5 v i/o mac power supply. 4, 15, 34 vdd12 1.2 v internal digital core voltage. 52 vdd12a 1.2 v 1.2 v analog po wer requiring additional pcb power supply filtering. 17 , pad (1) 1. exposed pad is on the bottom of the package. vss 0 v general device ground. table 83. miscellaneous pins (continued) pin name type description
vsc8601 datasheet pin descriptions revision 4.1 september 2009 page 90 6.2.7 power supply and associated function although certain function pins may not be used for a specific application, all power supply pins must be connected to their respective voltage input. table 85. power supply pins and associated function pins pins nominal voltage associated functional pins vdd33 3.3 v led[2:0], clkout, nres et, jtag (5), xtal1, xtal2, cmode, txvp, txvn, ref_filt, ref_rext vddiomicro 2.5 v, 3.3 v mdc, mdio, mdint, eeclk, eedat vddiomac 2.5 v, 3.3 v rxd, rx_ctl, rx_clk, txd, tx_ctl, tx_clk, nsreset
vsc8601 datasheet pin descriptions revision 4.1 september 2009 page 91 6.3 pins by name this section provides an alphabetical list of the vsc8601 pins. cmode0 35 cmode1 36 cmode2 37 cmode3 38 eeclk 10 eedat 9 led0 42 led1 41 led2 40 mdc 13 mdint 12 mdio 14 nc 48 nreset 8 nsreset 32 ntrst 7 oscen/clkout 43 pllmode 47 ref_filt 49 ref_rext 50 reg_en 44 reg_out 46 rx_clk 24 rx_ctl 18 rxd0 23 rxd1 22 rxd2 21 rxd3 20 tck 6 tdi 3 tdo 2 tms 5 tx_clk 26 tx_ctl 31 txd0 30 txd1 29 txd2 28 txd3 27 txvna 54 txvnb 56 txvnc 59 txvnd 61 txvpa 53 txvpb 55 txvpc 58 txvpd 60 vdd12 4 vdd12 15 vdd12 34 vdd12a 52 vdd33 1 vdd33 39 vdd33 51 vdd33 57 vdd33 62 vddiomac 16 vddiomac 19 vddiomac 25 vddiomac 33 vddiomicro 11 vddreg 45 vss 17 xtal1/refclk 64 xtal2 63
vsc8601 datasheet pin descriptions revision 4.1 september 2009 page 92 6.4 pins by number this section provides a numeric list of the vsc8601 pins. 1 vdd33 2tdo 3tdi 4 vdd12 5tms 6tck 7ntrst 8nreset 9eedat 10 eeclk 11 vddiomicro 12 mdint 13 mdc 14 mdio 15 vdd12 16 vddiomac 17 vss 18 rx_ctl 19 vddiomac 20 rxd3 21 rxd2 22 rxd1 23 rxd0 24 rx_clk 25 vddiomac 26 tx_clk 27 txd3 28 txd2 29 txd1 30 txd0 31 tx_ctl 32 nsreset 33 vddiomac 34 vdd12 35 cmode0 36 cmode1 37 cmode2 38 cmode3 39 vdd33 40 led2 41 led1 42 led0 43 oscen/clkout 44 reg_en 45 vddreg 46 reg_out 47 pllmode 48 nc 49 ref_filt 50 ref_rext 51 vdd33 52 vdd12a 53 txvpa 54 txvna 55 txvpb 56 txvnb 57 vdd33 58 txvpc 59 txvnc 60 txvpd 61 txvnd 62 vdd33 63 xtal2 64 xtal1/refclk
vsc8601 datasheet package information revision 4.1 september 2009 page 93 7 package information the vsc8601 package is a lead(pb)-free, 64-pin, plastic low-profile quad flat package (lqfp) with an exposed pad, 10 mm 10 mm body size, 1.4 mm body thickness, 0.5 mm pin pitch, and 1.6 mm maximum height. lead(pb)-free products from vitesse comply with the temperatures and profiles defined in the joint ipc and jedec standard ipc/jedec j-std-020. for more information, see the ipc and jedec standard. this section provides the package drawin g, thermal specifications, and moisture sensitivity rating for the vsc8601 device. 7.1 package drawing the following illustration shows the pack age drawing for the vsc8601 device. the drawing contains the top view, bottom view, side view, detail views, dimensions, tolerances, and notes.
vsc8601 datasheet package information revision 4.1 september 2009 page 94 figure 24. package drawing c ccc s l 0.25 r2 r1 e2 e1 e a b b 4x 4x e c d2 d1 d d 4.000 4.000 exposed pad dimensions and tolerances a2 a1 a l1 c seating plane 0 1 - 0 - 0.05 s 0 2 - 0 3 - gage plane see detail a h 48 49 64 32 17 33 116 1 64 16 17 48 49 33 32 reference minimum nominal maximum ddd m c a-b s d s bbb h a-b d aaa c a-b d - - - - a a1 a2 d d1 e e1 r2 r1 0 0 1 0 2 0 3 c l l1 s b e d2 e2 aaa bbb ccc ddd 1.60 0.15 1.45 0.05 1.35 1.40 12.00 10.00 12.00 10.00 0.08 0.08 0 o 0 o 11 o 11 o 0.09 0.45 0.20 0.17 0.20 7 o 13 o 13 o 0.20 0.75 0.27 3.5 o 12 o 12 o 0.60 1.00 0.20 0.50 7.50 7.50 0.20 0.20 0.08 0.08 top view bottom view side view detail a notes 1. all dimensions and tolerances are in millimeters (mm). 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. dimension b does not include dambar protrusion. allowable dambar protrusion does not cause the lead width to exceed the maximum b dimension by more than 0.08 mm.
vsc8601 datasheet package information revision 4.1 september 2009 page 95 7.2 thermal specifications thermal specifications for this device ar e based on the jedec standard eia/jesd51-2 and have been modeled using a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p pcb). for more information, see the jedec standard. to achieve results similar to the modeled thermal resistance measurements, the guidelines for board design described in the jedec standard eia/jesd51 series must be applied. for information about specif ic applications, see the following: eia/jesd51-5, extension of thermal test board standards for packages with direct thermal attachment mechanisms eia/jesd51-7, high effective thermal conductivity test board for leaded surface mount packages eia/jesd51-9, test boards for area array surface mount package thermal measurements eia/jesd51-10, test boards for through-hole perimeter leaded package thermal measurements eia/jesd51-11, test boards for through-hole ar ea array leaded package thermal measurements 7.3 moisture sensitivity this device is rated moisture sensitivity le vel 3 or better as specified in the joint ipc and jedec standard ipc/jedec j-std-020. for more information, see the ipc and jedec standard. table 86. thermal resistances ja (c/w) vs. airflow (ft/min) part order number jc jb 0 100 200 VSC8601XKN 18.5 (1) 6.4 (2) 1. simulated on the top of the mold compound with the exposed pad soldered to a ground pad on the pcb. 2. calculated on the exposed pad soldered to a ground pad on the pcb. 22 33 30 28
vsc8601 datasheet design considerations revision 4.1 september 2009 page 96 8 design considerations this section explains various issues associated with the vsc8601 device. 8.1 rx_clk can reach as high as 55% duty cycle issue: when register 23, bit 8 = 0 (no intern al clock skew) for rgmii, then the rx_clk duty cycle has been measured as high as 55%. implications: there is a possibility that the du ty cycle can go beyond this value, which then violates what is specified in the datash eet. this has only been observed when the skew setting is set to 0. workaround: avoid using an rgmii skew setting of 0. 8.2 first smi write fails after software reset issue: after applying software reset (using either register 0, bit 15 or the nsreset pin), the first subsequent smi write operation into register 4 (auto-negotiation advertisement) or register 9 (1000base-t control) does not work. this issue only occurs if the first smi write after software reset is into register 4 or 9. this issue does not occur if any kind of smi transaction (either read or write) is applied to any register between the time of the software reset and the smi write into register 4 or 9. implications: the phy may operate unexpectedly, because settings for registers 4 and 9 remain at the reset value. there are no such implications after either hardware reset or power-down events. workaround: writing ?0x0000? into register 31 after every software reset avoids this issue, and subsequent smi writes into register 4 or 9 succeed. 8.3 link-up issue in forced 100base-tx mode issue: while in the forced 100base-tx mode with the automatic crossover detection feature (hp auto-mdix) enabled, it can take up to several minutes for the link-up process between the vsc8601 device and a link partner that also has its automatic crossover detection feature enabled. the problem has not been observed in any other operation modes. implications: while working against some link partners, such as those by marvell, it can take up to several minutes for the link-up process to complete. workaround: when forcing 100base-tx mode, use the following script to alter the internal method that the vsc8601 uses to perform crossover detection. for more information, see phy api software and programmers guide, which is available on the vitesse web site at www.vitesse.com. phywrite (portno, reg_num(dec), 16_bit_unsigned_data(hex)) phywritemsk (portno, reg_num(dec), 16_bit_unsigned_data(hex), mask(hex))
vsc8601 datasheet design considerations revision 4.1 september 2009 page 97 phywrite (portno, 31, 0x52b5); // select internal register page phywrite (portno, 16, 0xa7f8); // request read of internal register phywritemsk (portno, 17, 0x0018, 0x0018); // set for forced 100base-tx phywritemsk (portno, 18, 0, 0); // necessary read & re-write register 18 phywrite (portno, 16, 0x87f8); // write back modified internal register phywrite (portno, 31, 0); // select main register page when returning from forced 100base-tx mo de to auto-negotiation mode, use the following script to restore the standard method that vsc8601 uses to perform crossover detection: phywrite (portno, 31, 0x52b5); // select internal register page phywrite (portno, 16, 0xa7f8); // request read of internal register phywritemsk (portno, 17, 0x0000, 0x0018); // set for auto-negotiation phywritemsk (portno, 18, 0, 0); // necessary read & re-write register 18 phywrite (portno, 16, 0x87f8); // write-back modified internal register phywrite (portno, 31, 0); // select main register page note it is not important which order is used for writes to the smi register with respect to writes to register 0, which disable and enable the auto-negotiation feature. 8.4 default 10base-t settings are marginal and cause mau test failure issue: default 10base-t settings are marginal for phy silicon and magnetic module variations. implications: it often causes the output 10base-t signal to violate the ieee waveform templates. workaround: during device initialization, use the following script. for more information, see phy api software and programmers guide , which is available on the vitesse web site at www.vitesse.com. phywrite (portno, reg_num(dec), 16_bit_unsigned_data(hex)) phyread (portno, reg_num(dec)) ~ -- logical not & -- logical and | -- logical or = -- assign value to variable phywrite (portno, 31, 0x52b5); // select internal register page phywrite (portno, 18, 0x9e); // necessary write of internal register phywrite (portno, 17, 0xdd39); // necessary write of internal register phywrite (portno, 16, 0x87aa); // necessary write of internal register phywrite (portno, 16, 0xa7b4); // necessary write of internal register reg = phyread (portno, 18); // read internal reg. and assign it to var. phywrite (portno, 18, reg); // necessary write of internal register reg = phyread (portno, 17); // read internal reg. and assign it to var. reg = (reg & ~0x003f) | 0x003c;// modify variable value phywrite (portno, 17, reg); // write back modified internal register
vsc8601 datasheet design considerations revision 4.1 september 2009 page 98 phywrite (portno, 16, 0x87b4); // necessary write of internal register phywrite (portno, 16, 0xa794); // necessary write of internal register reg = phyread (portno, 18); // read internal reg. and assign it to var. phywrite (portno, 18, reg); // necessary write of internal register reg = phyread (portno, 17); // read internal reg. and assign it to var. reg = (reg & ~0x003f) | 0x003e;// modify variable value phywrite (portno, 17, reg); // write back modified internal register phywrite (portno, 16, 0x8794); // necessary write of internal register phywrite (portno, 18, 0xf7); // necessary write of internal register phywrite (portno, 17, 0xbe36); // necessary write of internal register phywrite (portno, 16, 0x879e); // necessary write of internal register phywrite (portno, 16, 0xa7a0); // necessary write of internal register reg = phyread (portno, 18); // read internal reg. and assign it to var. phywrite (portno, 18, reg); // necessary write of internal register reg = phyread (portno, 17); // read internal reg. and assign it to var. reg = (reg & ~0x003f) | 0x0034;// modify variable value phywrite (portno, 17, reg); // write back modified internal register phywrite (portno, 16, 0x87a0); // necessary write of internal register phywrite (portno, 18, 0x3c); // necessary write of internal register phywrite (portno, 17, 0xf3cf); // necessary write of internal register phywrite (portno, 16, 0x87a2); // necessary write of internal register phywrite (portno, 18, 0x3c); // necessary write of internal register phywrite (portno, 17, 0xf3cf); // necessary write of internal register phywrite (portno, 16, 0x87a4); // necessary write of internal register phywrite (portno, 18, 0x3c); // necessary write of internal register phywrite (portno, 17, 0xd287); // necessary write of internal register phywrite (portno, 16, 0x87a6); // necessary write of internal register phywrite (portno, 16, 0xa7a8); // necessary write of internal register reg = phyread (portno, 18); // read internal reg. and assign it to var. phywrite (portno, 18, reg); // necessary write of internal register reg = phyread (portno, 17); // read internal reg. and assign it to var. reg = (reg & ~0x0fff) | 0x0125;// modify variable value phywrite (portno, 17, reg); // write back modified internal register phywrite (portno, 16, 0x87a8); // necessary write of internal register phywrite (portno, 31, 0); // select main register page
vsc8601 datasheet design considerations revision 4.1 september 2009 page 99 8.5 on-chip pull-up resistor violation issue: according to the ieee standard 802.3, the mdio pin on a slave device should be an open-drain pad type and drive a low va lue onto the mdio shared bus. the mdio shared bus should be pulled high with a pull -up resistor on the pcb or smi bus master. the vsc8601 device includes a 100 k pull-up on-chip resistor that violates this ieee specification. implication: the vsc8601 device requires an off-chip and on-chip pull-up resistor for the interface to operate correctly. the typical va lue of the off-chip resistor is relatively small at <1 k , which maintains a short rise time of the mdio signal. adding a 100 k pull-up on-chip resistor in parallel with the off-chip pull-up resistor, does not have any practical implications. workaround: no workaround is needed. 8.6 setting the internal rgmii timing compensation value issue: there are two inter-related registers to control the internal rgmii skew timing compensation. the finest level of control is through register 28e.15:12, which has four settings (0 ns, 1.4 ns, 1.7 ns, and 2.0 ns) for either rx or tx. alternatively, register 23.8 provides a simpler level of control (0 ns or 1.7 ns for both rx and tx) for compatibility with legacy vitesse phy software. a write to either register automatically affects the other so that they are logically consistent. however, this relationship means the legacy control of register 23.8 can potent ially overwrite the finer-level controls in register 28e. implication: if you intend to use the skew compensation settings in 28e, always write to this register after, not before, a write to register 23. for example, suppose register 23.8 is set to 1 (1.7 ns) and then register 28e.15:12 is set to 0101 (1.4 ns); the resulting delay is 1.4 ns. a subsequent write to register 23, even if bit 8 is kept as 1, automatically changes register 28e to 1010 (1.7 ns). workaround: before performing a write to re gister 23, first read and store the settings in register 28e. after writing to register 23, write the stored value back to register 28e. 8.7 10base-t harmonics at 30 mhz and 50 mhz marginally violate specification issue: the ieee 802.3 specification states th at in 10base-t mode, when the do circuit is driven by an all-ones, manchester-encoded signal, any harmonic measured on the td circuit must be at least 27 db below the fund amental. in vsc8601, this specification is marginally violated at 30 mhz and 50 mhz when this measurement is made under corner conditions. under nominal condit ions, this measurement meets the ieee specification limits. implications: this violation has no practical implication on the performance of the device. 10base-t mode has been validated to work without any issues with cables far exceeding the ieee-specified, worst-case limits. workaround: none required.
vsc8601 datasheet design considerations revision 4.1 september 2009 page 100 8.8 voltage overshoot when using on-chip switching regulator issue: the device?s on-chip switching regulator generates notable voltage overshoot. implications: the voltage overshoot from th e on-chip switching regulator may lead to device performance issues such as crc errors, jitter, or both. workaround: when using the on-chip regula tor, dampen the overshoot by adding a snubber circuit on the output of the regulator pins (reg_out). this circuit consists of a 15 resistor and 0.001 f capacitor connected in series to the reg_out pins and ground. for more information about the regulator circuitry connection, see vsc8601 design and layout guide , which is available on the vitesse web site at www.vitesse.com. 8.9 long link-up times ca used by noise on the twisted pair interface issue: the vsc8601 may experience longer link-up times during the link-up auto-negotiation process when there is si gnal noise coming from the link partner. implications: normally, the vsc8601 device successfully links during auto-negotiation when there is signal noise coming from the link partner. however, on rare occasions, the link-up time can be significantly in creased for successful auto-negotiation. workaround: during device initialization, it is strongly recommended that the following software script is implemented. for more information, see phy api software and programmers guide , which is available on the vitesse web site at www.vitesse.com. phywrite (portno, reg_num(dec), 16_bit_unsigned_data(hex)) phyread (portno, reg_num(dec)) ~ -- logical not & -- logical and | -- logical or = -- assign value to variable phy_write (portno, 31, 0x52b5); // select internal register page phy_write (portno, 16, 0xa7fa); // necessary write of internal register reg = phy_read (portno, 18); // read internal register and assign it to var. phy_write (portno, 18, reg); // necessary write of internal register reg = phy_read (portno, 17); // read internal register and assign it to var. reg = (reg | 0x0008); // modify variable value phy_write (portno, 17, reg); // write back modified internal register phy_write (portno, 16, 0x87fa) // necessary write of internal register phy_write (portno, 31, 0x0000); // select main register page
vsc8601 datasheet design considerations revision 4.1 september 2009 page 101 8.10 high vdd33 and low vddiomac supply issue: if vdd33 is set to the maximum allowed 3.3 v supply and vddiomac is set to the minimum allowed 3.3 v supply, the vsc8 601 device can experience performance issues. these issues generally occur in a lab environment and not in typical applications. implications: when vddiomac is set to 3.3 v, vdd33 and vddiomac cannot be sourced by two different 3.3 v supplies. workaround: if using vddiomac in 3.3 v mo de, use the same 3.3 v source supply as the vdd33, using a proper filtering scheme. for more information, see vsc8601 design and layout guide , which is available on the vitesse web site at www.vitesse.com.
vsc8601 datasheet ordering information revision 4.1 september 2009 page 102 9 ordering information the vsc8601 package is a lead(pb)-free, 64-pin, plastic low-profile quad flat package (lqfp) with an exposed pad, 10 mm 10 mm body size, 1.4 mm body thickness, 0.5 mm pin pitch, and 1.6 mm maximum height. lead(pb)-free products from vitesse comply with the temperatures and profiles defined in the joint ipc and jedec standard ipc/jedec j-std-020. for more information, see the ipc and jedec standard. the following table lists the ordering information for the vsc8601 device. table 87. ordering information part order number description VSC8601XKN lead(pb)-free, 64-pin, plas tic lqfp with an exposed pad, 10 mm 10 mm body size, 1.4 mm body thickness, 0.5 mm pin pitch, and 1.6 mm maximum height

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